i.MX8M Mini LPDDR4-3000 Trace length/delay matching

[SPEEDBIRD]

Hello,

I'm currently designing a custom PCB with the i.MX8M Mini using the LPDDR4-3000 as memory. I have multiple questions when it comes to routing the LPDDR4-3000 to the i.MX8M Mini.

I'm aware of the i.MX 8M Mini Hardware Developer's Guide document but still have a lot of questions. 

NOTE: I'm currently using Autodesk Fusion 360 and therefor I'm limited when it comes SI Simulations. I know Fusion 360 has a SI Simulation tool extension, but it's not really useful... 

My current design is using the exact same board stack up and trace widths (for controlled impedance) as the 8MMINILPD4-CPU (see figure 1 & 2 below). 

1. Is it sufficient enough if I only length match all signals to the DDR (note that I'm using Layer 1, 3 and 8 like in the 8MMINILPD4-CPU design)? See figure 3 below, Layer 1 = red, Layer 3 = yellow, Layer 8 = blue. All signals have an equal length of 868 mil.

2. If length matching is not sufficient I will have to time delay match. Do I have to include the pkg delays into these calculations?

3. Is there a rule of thumb for the Signal Propagation e.g. per 1mm about 6.7ps? 

4. With the current stack up, will I need to be very exact and calculate different signal propagation for signals in the third layer, because these are striplines and the signal is therefor slower than on microstrips?

Thanks in advance and help is much appreciated!

Regards,

SPEEDBIRD

[riteshmpatel]

Hi @SPEEDBIRD,

I hope you are doing well.

Please see the response to your queries below:

1. Is it sufficient enough if I only length match all signals to the DDR (note that I'm using Layer 1, 3 and 8 like in the 8MMINILPD4-CPU design)? See figure 3 below, Layer 1 = red, Layer 3 = yellow, Layer 8 = blue. All signals have an equal length of 868 mil.
[NXP]: If all the DDR signals mentioned in Section 3.4.2.1 i.MX 8M Mini LPDDR4-3000 routing recommendations of HDG document and all recommended guidelines are followed, then it is good to go.

2. If length matching is not sufficient I will have to time delay match. Do I have to include the pkg delays into these calculations?
[NXP]: Package delay of memory IC shall not be taken into consideration.

3. Is there a rule of thumb for the Signal Propagation e.g. per 1mm about 6.7ps?
[NXP]: One can refer to the below-mentioned link for refer of Signal propagation.
https://www.protoexpress.com/blog/signal-propagation-delay-pcb/

4. With the current stack up, will I need to be very exact and calculate different signal propagation for signals in the third layer, because these are striplines and the signal is therefore slower than on microstrips?
[NXP]: Yes, that is correct.

Thanks & Regards,
Ritesh M Patel