i.MX8M Mini DSE settings

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i.MX8M Mini DSE settings

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mpsotti
Contributor I

Hello,

regarding the i.MX8M Mini processor, I cannot find in the documentation (datasheet, reference manual, hardware guidelines) any reference to a fundamental parameter: the characteristic impedance of the GPIO pads depending on the value set in the pinmux control register (DSE bit). Only values such as x1, x2, x4, x6 are indicated, but not in reference to a characteristic R0, as specified for other NXP processors.

I’m experiencing some EMC-related issues on the SDIO lines, and having this parameter would be helpful to potentially test terminations, characterize the line, and perform simulations.

The only thing I found in the datasheet is the current specification at 1.8V and 3.3V under the "GPIO DC parameters," but based on the listed values, I get a minimum value of 1.8V / 9.6mA = 187.5 ohms, which seems extremely high for SDIO signals operating in SDR104 mode (208 MHz)!

mpsotti_1-1749805451681.pngmpsotti_1-1749805451681.png

Otherwise, I found on page 32 the resistance values for the DDR pads only. I would expect similar orders of magnitude for the SDIO peripheral pads.

mpsotti_0-1749805431676.pngmpsotti_0-1749805431676.png

 

IHere there are similar questions I found on the forum:

Solved: iMX8MP drive strength x1..x6 meaning - NXP Community

I.MX8M GPIO output impedance - NXP Community

but the answers are not well explained.. Could someone clarify if I’m missing something?

thank you.

 

 

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mpsotti
Contributor I

Hello, @Zhiming_Liu ,

Thank you for the reply but as i said in my question:

The only thing I found in the datasheet is the current specification at 1.8V and 3.3V under the "GPIO DC parameters," but based on the listed values, I get a minimum value of 1.8V / 9.6mA = 187.5 ohms, which seems extremely high for SDIO signals operating in SDR104 mode (208 MHz)!

mpsotti_0-1750661952226.pngmpsotti_0-1750661952226.png

 

Otherwise, I found on page 32 the resistance values for the DDR pads only. I would expect similar orders of magnitude for the SDIO peripheral pads.

mpsotti_1-1750661952222.pngmpsotti_1-1750661952222.png

 

From my experience that values are not the resistive impedance at the driver's pad of the processor.. They just seems like some test currents injected in the pads in order to get minimum voltage values (Voh).

I've always found characteristic impedance values of pads varying drive strength in every NXP processor datasheet.. i don't know why for IMX8M Mini or Plus this important information as been completely omitted for General Purpose IO. 

 

 

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Zhiming_Liu
NXP TechSupport
NXP TechSupport

Hi @mpsotti 

1. It was confirmed that NXP does not have a similar table for usdhc internally either. If the usdhc is strictly designed to have a single-ended impedance of 50 ohms, there should be no similar problem. Please check if all uSDHC signals had been routed in the same length with 50Ohms impedance.

2. Using DC parameters to estimate impedance of high speed signals is inaccurate.

3. If you don't want to confirm the problem by debugging the hardware layout, you can do SI emulation.


Best Regards,
Zhiming

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Zhiming_Liu
NXP TechSupport
NXP TechSupport

Hi @mpsotti 

The “Test Conditions” column of Table 26, “GPIO DC Parameters,” lists the exact current values (e.g., mA) for different DSE settings in the order of X1, X2, X4, and X6 for both 1.8V and 3.3V supply voltages.

Zhiming_Liu_0-1750038160300.pngZhiming_Liu_0-1750038160300.png

For SDIO interface, did you design the SDIO interface according to the specifications in the hardware design documentation? Does this problem only occur during EMC testing, or does it affect the normal use of the SDIO?


Best Regards,
Zhiming

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