We are developing a smart device application on Visual studio for i.MX7D device using TORADEX SDK and SOM on Colibri i.MX7 EVK board with Win CE 7.
We are using EIM interface for one of our application and found that, When we slow down the EIM clock using( 3.90625 MHz ) PRE_PODF bits of CCM_TARGET_ROOT83 register( In our case eim clock source selected is 125 MHz and setting PRE_PODF to divide by 8 and BCD to Divide by 4), We observed that sometimes during EIM register initialisation, registers does not get updated by the values we assign to them. In fact with these settings CS0RCR1 or CS0WCR1 gets updated with some different settings.
However if we set the EIM clock to higher frequency 15.625 MHz( eim clock source selected is 125 MHz and setting PRE_PODF to divide by 2 and BCD to Divide by 4 ) then there is no issue with register settings and it works as expected.
The behaviour is unpredictable in first case.
Please find below the EIM Initialization code for your reference and review:
// EIM clock root and clock gate registers
#define CCM_BASE_ADDRESS 0x30380000
#define CCM_CCGR22 0x30384160
#define CCM_TARGET_ROOT83 0x3038A980
#define CS0_REGISTER_BASE_ADDRESS 0x30BC0000
#define CS0_REGISTER_MEMORY_SIZE 256
clkRegs = (DWORD* )Map_MapMemory(CCM_BASE_ADDRESS, 0x10000);
targetAddrCCM_CCGR22 = clkRegs + (CCM_CCGR22 - CCM_BASE_ADDRESS)/4;
*targetAddrCCM_CCGR22 &= ~0xFFFFFFFF;
targetAddrCCM_CCGR22 = clkRegs + (CCM_CCGR22 - CCM_BASE_ADDRESS)/4;
*targetAddrCCM_CCGR22 |= 0x03;
LOG_MSG("CCGR reg: 0x%08X\n",*targetAddrCCM_CCGR22 );
targetAddrCCM_TARGET_ROOT83 = clkRegs + (CCM_TARGET_ROOT83 - CCM_BASE_ADDRESS)/4;
*targetAddrCCM_TARGET_ROOT83 |= 0x10000000;//clock root enable
*targetAddrCCM_TARGET_ROOT83 |= 0x06000000;//clock source 125MHz
*targetAddrCCM_TARGET_ROOT83 |= 0x00070000;//Predivider
//Bit 18 - 17 - 16
//0x00000000; // predivider 1
//0x00010000; // predivider 2
//0x00020000; // predivider 3
//0x00030000; // predivider 4
//0x00040000; // predivider 5
//0x00050000; // predivider 6
//0x00060000; // predivider 7
//0x00070000; // PreDivider 8
LOG_MSG("\nCCM Target Root reg: 0x%08X\n",*targetAddrCCM_TARGET_ROOT83 );
// Map EIM registers
pEimReg = (volatile tEIM_CSP_WEIM_REGS *)Map_MapMemory( CS0_REGISTER_BASE_ADDRESS, CS0_REGISTER_MEMORY_SIZE );
// Configure EIM registers in Synchronous Multiplexed mode
Map_MemoryWrite( (void *)&pEimReg->EIM_CS0GCR1, 0x10117C3F, 32 );// BCD Divide by 4(Bit 13-12 = 11 )
Map_MemoryWrite( (void *)&pEimReg->EIM_CS0GCR2, 0x00001000, 32 );
Map_MemoryWrite( (void *)&pEimReg->EIM_CS0RCR1, 0x03000000, 32 );
Map_MemoryWrite( (void *)&pEimReg->EIM_CS0RCR2, 0x00000000, 32 );
Map_MemoryWrite( (void *)&pEimReg->EIM_CS0WCR1, 0x01000000, 32 );
Map_MemoryWrite( (void *)&pEimReg->EIM_CS0WCR2, 0x00000000, 32 );
LOG_MSG("CSxGCR1 main reg: 0x%08X\n",pEimReg->EIM_CS0GCR1);
LOG_MSG("CSxGCR2 main reg: 0x%08X\n",pEimReg->EIM_CS0GCR2);
LOG_MSG("CSxRCR1 main reg: 0x%08X\n",pEimReg->EIM_CS0RCR1);
LOG_MSG("CSxRCR2 main reg: 0x%08X\n",pEimReg->EIM_CS0RCR2);
LOG_MSG("CSxWCR1 main reg: 0x%08X\n",pEimReg->EIM_CS0WCR1);
LOG_MSG("CSxWCR2 main reg: 0x%08X\n",pEimReg->EIM_CS0WCR2);
LOG_MSG("WCR main reg: 0x%08X\n",pEimReg->EIM_WCR);
LOG_MSG("WIAR main reg: 0x%08X\n",pEimReg->EIM_WIAR);
LOG_MSG("DCR main reg: 0x%08X\n",pEimReg->EIM_DCR);
LOG_MSG("DSR main reg: 0x%08X\n",pEimReg->EIM_DSR);
Please guide us to find the root cause of this issue.
Regards
Bipin Kumar
