i.MX6UL, MMDC_MDMISC register

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i.MX6UL, MMDC_MDMISC register

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tomasjun
Contributor I

Hello,

please I need describe exactly bit 31 of MMDC_MDMISC register,

CS0_RDY: 0 Device in wake-up period / 1 Device is ready for initialization

What is "normal state" -  Wake-up or Device ready ... ?

Thank you for cooperation.

Tomas

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tomasjun
Contributor I

Thank you very much for your answer!

Tomas

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gusarambula
NXP TechSupport
NXP TechSupport

Hello Tomas Jun,

The CS0_RDY bit is cleared at reset or during deep power-down entry of the memory. This bit is set after the wake-up period, when the memory is ready for transfers which you may call normal state.

I hope this information helps!

Regards,

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