i.MX6UL ENET2: Relationship between TX_CLK and external data signals

[johannesdev]

Hi,

I'm trying to find out the time-relationship between TX_CLK and the data signals of the ENET2 instance of the i.MX6UL SoC, whereas TX_CLK (50M_REF) is generated, i.e., output by the SoC. The datasheet shows the following diagram:

ENET_CLK is referred as input (to the SoC) in the diagram rather than as output in my application. So my question: Is this diagram with all of its timing values also valid when ENET_CLK outputs the 50Meg RMII ref clk?

Thanks and best regards,
Johannes

[Yuri · Accepted solution]

@johannesdev 
Hello,

  The i.MX 6UL RMII reference clock (ENETx_REF_CLKx) can be configured as input or output. In the case of output, ENET reference internal clock is also provided for internal ENET circuits in parallel with output one. In this sense output ENETx_REF_CLKx is the same as internal (input) ENET reference clock.

Regards,
Yuri.