About Non-Gated Clock Mode issue of the Parallel CSI module on the iMX series MPU.

[vikenzhou]

Hi, I am have a question about the Parallel CSI module, hope here can get answer, thank you!

When MPU is running  in Non-Gated Clock Mode, because the HSYNC signal will be ignored,
How know a line the number of pixels, it is possible using the clock edge to latched data;  if so,  in this Parallel_CSI_TX side, the pixel data of a line can many discontinuous clock cycles to send out ?

2，The Data_EN signal in the Parallel_CSI_RX is necessary? The figure 19 on page758 of document  (IMX6ULLRM.pdf), Here is no use this Data_EN signal.

3, When sending a line of pixels, is the need for a continuous clock to send a line, or send a line of pixels can be discontinuous .

Please see below the figure,  thank you!

[igorpadykov]

Hi vikenzhou

1. image length, width can be programmed with register CSI_CSIIMAG_PARA,
described in sect.19.7.13 CSI Image Parameter Register (CSI_CSIIMAG_PARA)

Reference Manual

2. in rev.1 Reference Manual there is no Data_EN :

i.MX 6ULL Applications Processor Reference Manual

3.   per description in sect.19.4.3 Non-Gated Clock Mode

"The PIXCLK signal is inactive (states low)
until valid data is ready to be transmitted over the bus."

Best regards
igor