Typically, the RGMII Gigabit Ethernet PHY interface provides an analog voltage regulator (typically, installed on PHY IC) that makes the appropriate supply voltage for the PHY (and corresponding CPU interface) I/O signals. The typical values of this voltage (depending on implementation) are 1.5V, 1.8V or 2.5V. Powering the whole interface from 3.3V may get it out of spec. For example, please refer to the schematics of the i.MX6SoloX SABRE SD board, available on the Freescale web site:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=RDIMX6SABREBRD&fpsp=1&tab=Design_Tool...
Have a great day,
Artur
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------