i.MX6QSD SATA suspend/resume

[mileswang]

Hello,

I met some problem about SATA suspend/resume when i.MX6QSD enter/exit deep sleep mode. Below is the flow:

1. Send command ATA_CMD_STANDBY_IMMEDIATE (0xE0) to SSD, SSD enter standby mode.

2. SATA_P0CMD[ICC]=6. Put SATA PHY to SLUMBER mode.

3. i.MX6QSD enter deep sleep mode (DSM).

4. Wakeup by input of UART.

5. ARM Cortex A9 exit from WFI and start to run.

6. SATA_P0CMD[ICC]=1. Request a transition of the interface into the active state.

7. Delay 10ms.

8. Send command ATA_CMD_IDLE_IMMEDIATE(0xE1) to SSD.

My questions:

1. PHY from ACTIVE to SLUMBER (step 2), are SATA_P0SERR[DIAG_X] and SATA_P0IS[PCS] bits set?

2. PHY from SLUMBER to ACTIVE (step 6), are SATA_P0SERR[DIAG_X] and SATA_P0IS[PCS] bits set?

3. Do SATA registers need to be saved befroe DSM and restored after DSM?

4. Do SATA need to re-intialize after DSM? Remove SSD and then attach it again.

5. Is above flow OK?

6. Do you have any document about SATA suspend/resume?

Thanks,

Miles

[igorpadykov]

Hi Miles

seems this is caused by erratum ERR007966 SATA:

SATA speed negotiation fails after suspend and resume

i.MX6DQ Errata   http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf

Best regards

igor

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[mileswang]

Hi Igor,

About Workaround #2:

Add a SATA PHY CR-RESET in the resume through software. This will reset the

PHY and allow the link to resume.

After resume is initiated, the following steps are required:

• Wait a minimum of 100 us to allow the MPLL time to lock

• Perform the PHY CR reset

• Wait an additional 100 us to allow the RX PLL to lock (polling CR register bit

‘rx_pll_state’

How to perform the PHY CR reset? is SATA_P0PHYCR CR register?

Software workaround#2 has been implemented into Linux L3.10.17_1.0.0_GA release. Can you tell me which file is changed for workaround#2?

Thanks,

Miles