i.MX6DQ CSI gated mode VSYNC

[herveschmitt]

We are trying to support a new camera on CSI0 (parallel sensor interface). Our sensor works in ITU601 mode that looks like the "gated" mode, except that HSYNC is active during the complete duration of an image (starting 16 pixel clock cycles before the first HSYNC gets active, and stopping 16 pixel clock cycles after the last HSYNC gets inactive).

It doesn't match with the normal usage of the gated mode (described at §37.4.3.6.2 of the RM) but should work if the VSYNC is edge-triggered (either on the rising or the falling edge).

If the level of VSYNC is taken into account, it probably won't work.

Has anyone used gated mode with a similar signal VSYNC ?

Is there any internal information on GATED MODE indicating if such a VSYNC signal could also work ?

Thanks for any feedback.

[igorpadykov · Accepted solution]

Hi Herve

you are right, VSYNC is edge-triggered and

this is mentioned in sect.4.11.10.2 Sensor Interface Timings

i.MX6DQ Datasheet (rev.4, 7/2015)

http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf

Best regards

igor

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[herveschmitt]

OK, VSYNC is latched on the rising edge when working in GATED MODE.

§4.11.10.2.2 of http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf seems wrong concerning data sampling : "Data is latched at the rising edge of the valid pixel clocks." Chronogramms clearly show that data sampling occur on the falling edge of the pixel clock.

What are the blanking constraints when working in GATED MODE ?

I didn't find information on this topic in the manuals... To be more precise, this question could be split in several sub-questions :

• When the VSYNC signal rising edge occurs, how many pixel clock cycles [min..max] should we have before asserting HSYNC ?
• At the end of a line, when HSYNC is deasserted, how many pixel clock cycles [min..max] should we have before re-asserting HSYNC ?
• At the end of the last line, when HSYNC is deasserted, how many pixel clock cycles [min..max] should we have before the next rising edge of VSYNC ?
• Do the above "blanking constraints" depend on the resolution, format, or pixel clock frequency ?

For information, here is a capture of our VSYNC rising edge followed by HSYNC assertion. Signals are a bit noisy due to cables soldered on our PCB. Is there anything wrong explaining why it doesn't work (320x200 in YUV422) ?

[igorpadykov]

one can look at docx on link below

About HSYNC timing of CSI input in i.MX6DQ.

also had you set correct CSI_DATA_EN as described below

IPU2 for CSI parallel camera

~igor