Using the mainline kernel on i.MX6 Solo with connected LVDS panel, I see artifacts that look like some data lines to the LDB are one pixel clock late. These are especially apparent in horizontal red-to-black and black-to-red gradients, where one can see one pixel wide light or dark vertical stripes in regular intervals, depending on the direction of the gradient.
On one device with a 24-bit SPWG LVDS panel, the artifacts only appear in the red channel, and only when driving the LDB LVDS0 channel from IPU DI0. When switching to IPU DI1, the artifacts disappear completely. The DI pixel clock is synchronized to the LDB_DI clock, which is sourced from PLL5 in each case.
On another device with a 18-bit SPWG LVDS panel, the artifacts are stronger, appear also in the blue and green color channels, and are also visible when switching to DI1. When rendering 1-pixel wide vertical gradients, these don't appear as a straight line, but are shifted or spread over two pixels horizontally, depending on the brightness value. On this hardware, replacing the i.MX6S CPU module with an otherwise identical i.MX6Q CPU gets rid of the artifacts. What could be the cause of this behaviour?
