i.MX6 NAND Timing Settings

[scott10]

Hello i.MX Community,

My team is working to optimize our i.MX6 NAND bus to maximize throughput while maintaining good margins. We are using the IMX6DQRM Rev. 3 for reference and we have a few questions we could use your help to answer:

[Q1]

What does the dsample_time parameter in the m_NandTiming array (Table 8-11) physically map to? Does it get used by the Boot ROM for raw NAND (Single Data Rate)?

• I see this is set to a default data_sample_time of 6 in kobs_ng's dot-kobs file, but there doesn't appear to be any other reference to it in any i.MX6 documentation or our NAND part's datasheet.
• Additionally, if I modify this parameter, update the FCB table in NAND, and then dump the registers after booting from NAND, I don't see any GPMI register changes.

[Q2]

Can you please confirm the m_NandTiming parameters for data_setup, data_hold, and address_setup are a 1:1 mapping with the bit fields in the GPMI_TIMING0 register? For example, if I want a data_hold equal to 10 GPMICLK cycles, should I set each parameter to 10 (0xA)?

[Q3]

Can you please confirm the Toggle Mode parameters in the FCB table (e.g. TMSpeed, TMTiming1_BusyTimeout) are ignored when using raw NAND (Single Data Rate).

• If so, I would also assume the GPMI registers these values set are also ignored when using raw NAND.

Thanks,

Scott

[art]

A1. Yes, these m_NandTiming parameters are used by the Boot ROM code to configure the NAND Flash Single Data Rate access timings for boot. Also, they can be used by secondary bootloader software when the control is passed to it.

A2. Yes, the m_NandTiming parameters for data_setup, data_hold, and address_setup are a 1:1 mapping with the bit fields in the GPMI_TIMING0 register.

A3. Yes, the Toggle Mode parameters in the FCB table (e.g. TMSpeed, TMTiming1_BusyTimeout) are ignored when using raw NAND (Single Data Rate).

Have a great day,
Artur

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[kreg]

Artur et.all,

In relation to A2 above, you say parameters for data_setup, data_hold, and address_setup are a 1:1 mapping with the bit fields in the GPMI_TIMING0 register. So if the GPMI clock is 68.57MHz (14.58ns) and we set these to 10, then we get a resultant time of 145.8ns? We are trying to track down some possible NAND timing issues and understanding this mapping is crucial to our analysis.

Thanks,

Kreg

[scott10]

Hi Artur,

Thank you for the answers! We have two follow-up questions:

1. Could you please clarify what the dsample_time parameter actually is?
   • From reviewing multiple datasheets, this doesn't appear to be a industry standard parameter/term.
2. Do you know what reference part was used for developing the kobs-ng tool and its sample configuration file (dot-kobs)?
   • If so, we may be able to use the part's datasheet to figure out from which parameter dsample_time was derived.

Thanks,

Scott