i.MX6 IPU couneter#1 and PIN1

[sugiyamatoshihi]

Hi, 

I tried to monitor IPU2_DI0_SW_GEN0_1 counter #1 signal.  Then I set PAD name NAND_RB0 as ALT1 IPU2_DI0_PIN01, but no signal came out. 

Is it possible to monitor counter#1 of PU2_DI0_SW_GEN0_1 by IPU2_DI0_PIN01?

Other PIN2, PIN3, PIN15 can be monitored as HSYNC ,VSYNC and DRDY.

Could you teach how to monitor counter#1 signal?

Best Regards,

Sugiyama 

[igorpadykov]

Hi Sugiyama 

please look at example

i.MX53: How to move VGA external HSYNC and VSYNC signals to different pins? 

PIN2, PIN3, PIN15 are supported in NXP software and this is described in Table 68.

Video Signal Cross-Reference i.MX6DQ Datasheet

http://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf

Note, writing ipu microcodes (wiriting custom codes for ipu couneter#1 and PIN1 waveforms)

is not supported and one can apply to NXP Professional Services to develop them:

http://www.nxp.com/support/nxp-professional-services:PROFESSIONAL-SERVICE

Best regards
igor
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[sugiyamatoshihi]

Hi, Igor,

Thank you for the answer. I understood PIN1 doesn't output counter#1 timing.

It is OK, I just would like to compare conter#1 and counter #2 signal. Because when counter #1 use for Vsync ( di0_run_resolution_3 in SW_GEN0_3), that looks Vsync signal, but if counter#2 use for Vsync, PIN3 output changes Low/Hi by each V timing like Field alternate signal. I expect the waveform is the same when both di0_run_value_m1_1 and di0_run_value_m1_2 use the same displays clock and resister value.

Best Regards,

Sugiyama