i.MX6 Ethernet Problem

[PaulDeMetrotion]

I am building a Linux kernel for a custom BSP using the i.MX6Q. I cannot get ethernet to work at all. Using an emulator I have been able to determine that nthe ethernet clock is getting dsiabled when the uImage is loaded. All the ethernet registers are cleared. Does anybody know how to enable the ethernet functionality of the i.MX6? The Phy device is an KSZ9031. Thanks.

[marktwainjr]

Hello,

I am having similar problem with imx6q for ENET driver test. Freescale's uboot does detect ethernet as FEC0 and link is shown UP and PING test can be performed from u-boot prompt, but on kernel link shows UP but can not perform PING test. I have above phy rework code in place.

How to check if PHY/ENET get correct clock? PHY is detected as Ar803x

Any guidence?

MT

[PaulDeMetrotion]

SOLVED: Found that we had a wrong resistor value for the KSZ89031. Everything works great now.

[PaulDeMetrotion]

No the command line did not include this and adding it fixed the issue of the initilaization function not running! Thanks.

I still cannot connect to the network. During boot the console displays the following after the fec is added:

eth0: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=1:00, irq=-1)

PHY status = 0x7949 (I added this comment to verify execution)

It then boots a little bit more and then pauses for almost a minute and displays this:

IP-Config: Guessing netmask 255.0.0.0

IP-Config: Complete:

     device=eth0, addr=124.0.0.0, mask=255.0.0.0, gw=255.255.255.255,

     host=124.0.0.0, domain=, nis-domain=(none),

     bootserver=255.255.255.255, rootserver=255.255.255.255, rootpath=

Why is a generic PHY being selected instead of the KSZ9031? Am I missing some configuration information?

[LeonardoSandova]

Better to ask this simple question: does the kernel command line include the 'ip=dchp' parameter?

[PaulDeMetrotion]

Anbody out there?

More data:

I have found that the driver is loaded and initialized properly. The driver itself turns off the clock:

        /* Carrier starts down, phylib will bring it up */
        netif_carrier_off(ndev);
        clk_disable(fep->clk);

It appears that the phy will reenable the clock. Don't know how. As mentioned the PHY is a KSZ9031. I have the following code within my kernel build:

static int mx6q_sbc35_c398_fec_phy_init(struct phy_device *phydev)

{

unsigned short val;

/* To enable AR8031 ouput a 125MHz clk from CLK_25M */

phy_write(phydev, 0xd, 0x7);

phy_write(phydev, 0xe, 0x8016);

phy_write(phydev, 0xd, 0x4007);

val = phy_read(phydev, 0xe);

val &= 0xffe3;

val |= 0x18;

phy_write(phydev, 0xe, val);

/* Introduce tx clock delay */

phy_write(phydev, 0x1d, 0x5);

val = phy_read(phydev, 0x1e);

val |= 0x0100;

phy_write(phydev, 0x1e, val);

/*check phy power*/

val = phy_read(phydev, 0x0);

if (val & BMCR_PDOWN)

     phy_write(phydev, 0x0, (val & ~BMCR_PDOWN));

return 0;

}

static struct fec_platform_data fec_data __initdata = {

.init = mx6q_sbc35_c398_fec_phy_init,

.phy = PHY_INTERFACE_MODE_RGMII,

};

Need to determine if the PHY is being intialized properly.

[PaulDeMetrotion]

The function mx6_clocks_init disables many of the internal function clocks. I assume the driver is supposed to enable the clock later when required, but I never see this happening. My boot console log does indicate that the FEC Ethernet Driver was loaded. Anybody have an idea why the clock never gets enabled? Is there a setting in the config file that needs to be programmed properly?