i.MX6 DMFC FIFO size

[sugiyamatoshihi]

Hi, 

I have a question about DMFC FIFO size of i.MX6 IPU.

There is a description in reference manual, "The DMFC's write FIFO is built of 1024 entries of 128-bits each."

1. Does this FIFO size means 512 entry x 128bit(4words) instead of All(512x128 words) of dmfc_fifo_size_5c description?

2. Does FIFO separate two planes as 512 entry x 128bit fro 1024 x128bit?

Best Regards,

Sugiyama

[b36401]

Here is a misprint in the table you quoted. It means 128-bits lines.

Have a great day,
Victor

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