i.MX6 Continuous BCLK

[zeahr]

Hi, if I follow the initialization flow for Continuous BCLK setting of EIM interface, does the BCLK output pin continues to produce clock even if the EIM access is not in synchronous mode? or  no EIM access at all. Because, there is a note written on page 996 of IMX6SDLRM.pdf that BCLK stops toggling when burst access is terminated.

The reason that I want the BCLK to be continuous at all time is because I want to use BCLK as a reference clock for FPGA.

Reference document, IMX6SDLRM.pdf,  i.MX 6Solo/6DualLite Applications Processor Reference Manual, Rev. 1, 04/2013.

Thanks. Rogelio

[Yuri]

  Really there are two options to have a free-running EIM clock for cases, when the EIM is used to communicate with a FPGA.
To meet such requirement, the Continuous (non stop) BCLK feature (documented in the RM) was added and EIM_ACLK_FREERUN - as

an alternative.

[zeahr]

Since  EIM_ACLK_FREERUN is an input pin, therefore the source clock is from FPGA (or from Oscillator) to i.MX6 for EIM communication?

If EIM_ACLK_FREERUN is used for FPGA communication, is BCLK not necessary duirng Burst Clock Mode (Synchronous Mode) access?

Thank you.

[Yuri]

ACLK may be considered as input reference internal clock for the EIM.

BCLK may be considered as output clock for external synchronous devices.

Some external devices (as FPGA) requires continuous clock. Basically

this may be provided via CONT_BCLK_SEL bit in EIM_WCR.

[borissnajder]

I'm also trying to connect a FPGA to the i.MX6 processor, and I'm having same problem. However, our intention is to migrate at some point from Solo/DualLite to the i.MX6Dual. But, in a IMX6DQRM there is no such option as EIM_ACLK_FREERUN input pin. Is this feature supported on the Dual version or only on Solo/DualLite.

Also, I would appreciate some clarification on continous mode. So, BCLK can be in free running mode without EIM_ACLK_FREERUN pin used. But, if EIM_ACLK_FREERUN pin is used than internal EIM clock is synchronized to this clock using a DLL?

Thank you.

Boris Snajder

[Yuri]

Really the iMX6Q does NOT support continuous BCLK.

This is main difference between EIM module of the i.MX6 DQ and i.MX6 SDL.

[norishinozaki]

Hello Yuri,

Please let me clear how to get a free-running EIM clock.

The Continuous BCLK is the only way for getting a free-running EIM clock, and the EIM_ACLK_FREERUN input pin can be used for EIM to run syncronus with the external device such as FPGA which needs reference clocks externally?

Best regards,

Nori Shinozaki

[Yuri]

IMX6 DQ  does NOT support continuous BCLK. I mean we cannot guarantee 

proper synchronization between internal (AXI) and external BCLK clocks, when
EIM_WCR[BCM] is set.

~Yuri.

[norishinozaki]

Hello Yuri,

I wanted to hear about the case of iMX6 S/DL.

What's the case?

Best regards,

Nori Shinozaki

[Yuri]

  Please refer to section 22.5.1 (Continuous BCLK) of the i.MX6 SDL RM regarding operation

under continuous BCLK MODE.  BCLK is i.MX6 output clock.  

~Yuri.

[norishinozaki]

Thanks Yuri,

The EIM_ACLK_FREERUN input can be used as internal EIM_ACLK?

There are few descriptions on EIM_ACLK_FREERUN.

Best regards,

Nori Shinozaki

[norishinozaki]

Yuri,

This is the reference. "AXI clock signal" is the only explanation.

[Yuri]

   Basically, to meet requirements to have a free-running EIM clock for cases,

where customers used the EIM to communicate with an FPGA, design added
the Continuous BCLK feature and this EIM_ACLK_FREERUN as an alternative.

  But there is no more information and hardware specs about this signal.

~Yuri.

[norishinozaki]

Yuri,

As you wrote EIM_ACLK_FREERUN as an alternative to Continous BCLK, it sounds like it's an output pin...

However in the RM...

Anyway the information is too few to use the pin whatever the funtion it is.

Best regards,

Nori Shinozaki

[Yuri]

Anyway the information is too few to use the pin whatever

> the function it is.

Yes. this is what I want to say.

~Yuri.

[keitanagashima]

Hi Yuri,

Is it possible to support the Continuous BCLK in i.MX6SoloLite?

(Should one set only CONT_BCLK_SEL bit in EIM_WCR?)

The external FPGA requires continuous clock, too.

Best Regards,

Keita

[Yuri]

  Yes, please refer to section 20.5.1 (Continuous BCLK) of the i.MX6 SL RM.

http://cache.nxp.com/files/32bit/doc/ref_manual/IMX6SLRM.pdf

Regards,

Yuri.

[keitanagashima]

Dear Yuri,

Hello.

Thank you for your reply. OK. I got it.

Best Regards,

Keita

[norishinozaki]

Hello Yuri,

Thank you for answers.

Let's close this thread.

Best regards,

Nori Shinozaki