i.MX53 DDR3 Controller Timing

[amanueltibebu]

I'm running Mentor Graphics HyperLynx SI to simulate the DDR3 layout on the i.MX53 QSB design. I'm doing this so I can compare these results to our custom design's results. I looked in the IMX53AEC document to figure out the controller timings but I didn't have all of the data I needed for the HyperLynx tool. However, there was a DDR3 controller timing module already provided with the software (attached). Are the timing parameters set in this file for the 800MHz case correct? If not, could you provide me with the correct values or point me to a document where I could find (or calculate) them.

Original Attachment has been moved to: ddr3_ctl.v.zip

[igorpadykov]

Hi Amanuel,

Freescale provides processor ibis pads data on link below

IMX53IBIS : i.MX53 IBIS File

i.MX535: i.MX535 Multimedia Applications Processor

Usage is described in Chapter 3 "Understanding the IBIS Model"

i.MX53 System Development User’s Guide (rev.1, 3/2011)

<http://www.freescale.com/files/32bit/doc/user_guide/MX53UG.pdf>

But processor DDR controller (ESDCTL) timing models are not available.

[sherry_zahid]

Sorry for replying to an old thread but the link to the IBIS models no longer works. I also require the latest IBIS model file. Would anyone be able to update this and provide a new link?