i.MX257: USB Host1 registers always read Zero

[sayan]

Hi,

I am preparing an USB driver for a board with iMX257 chipset.

I can read the register default values for OTG registers. But the Host1 registers are not in default values. All the values are read as Zero. Writing on those offset (0x0200 - 0x03A8) is also not reflecting. Whereas it is found that Host2 registers are in default values (though Host2 is not routed out).

I have set the hclk_usbotg clock. I wonder if any other clock setting is required for this or there may be some other setting. Is anyone having any idea? According to my understanding the usb_clk is enabled by default (Reason: By default usb_clk uses UPLL output as reference clock and UPLL is enabled by default).

I am stuck in the development.

Thanks in advance.

Regards,

Sayan Mukherjee

[igorpadykov]

Hi Sayan

please find attached arc_otg.h file from
linux/arch/arm/plat-mxc/include/mach/
 
Best regards
igor

[sayan]

Hi igor,

Thanks for the file. But could you please spend a bit time in the following with YES or NO:

According to my understanding

1. OTG core is available in iMX257 at offset 0x0000       (Yes / No)
2. HOST1 core is NOT available in iMX257                     (Yes / No)
3. HOST2 core is available in iMX257 at offset 0x0400   (Yes / No)

 where base address is 0x53FF4000.

According to the reference manual, there is no mention of Host2. But if we work using Host2

1. Which port shall we use in Armadillo440?  Upper?       (Yes / No)
2. Is Host2 routed out for communication?                        (Yes / No)

There exist stack of two USB ports. 

From NXP support I got a reply that Host2 is non-functional in iMX257. 

Regards,

Sayan

[igorpadykov]

Hi Sayan

i.MX25 has only two on-chip USB ports, one otg and one host port
Host 2 with registers under 0x400.

Best regards
igor

[igorpadykov]

Hi Sayan

right.
0x400 can be found in ltib linux sources: linux/arch/arm/plat-mxc/include/mach/arc_otg.h
Board Support Packages (4)
Linux 2.6.31 Source Code Files 2009.12 Release support i.MX23, i.MX25, i.MX51. (REV 2009.12)
http://www.nxp.com/products/power-management/pmics/pmics-for-i.mx-processors/i.mx25-product-developm...

Best regards
igor

[sayan]

Hi igor,

I did not find linux/arch/arm/plat-mxc/include/mach/arc_otg.h file in the "Linux 2.6.31 Source Code Files 2009.12 Release support i.MX23, i.MX25, i.MX51. (REV 2009.12)". 

According to my understanding

1. OTG core is available in iMX257 at offset 0x0000       (Yes / No)
2. HOST1 core is NOT available in iMX257                     (Yes / No)
3. HOST2 core is available in iMX257 at offset 0x0400   (Yes / No)

 where base address is 0x53FF4000.

According to the reference manual, there is no mention of Host2. But if we work using Host2

1. Which port shall we use in Armadillo440?  Upper?       (Yes / No)
2. Is Host2 routed out for communication?                        (Yes / No)

There exist stack of two USB ports. 

From NXP support I got a reply that Host2 is non-functional in iMX257. 

Regards,

Sayan

[igorpadykov]

Hi Sayan

you are right, i.MX25 has only Host 2 registers under 0x400. There are

two on-chip USB ports with PHY,  please check i.MX25 datasheet

Table 2. i.MX25 Parts Functional Differences

http://www.freescale.com/files/dsp/doc/data_sheet/IMX25CEC.pdf 

High Speed USB OTG with HS PHY

High Speed USB Host with FS PHY

Best regards
igor
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[sayan]

Hi igor,

Thanks for your reply.

This document is for iMX28. But I am working in iMX257.

Moreover, I have to work with the Host core. As only one Host core is routed out i.e the Host1 core, so I need to work with theregisters from offset 0x0200. Is this not feasible? I mean is there some special settings needed?

Regards,

Sayan

[igorpadykov]

Hi Sayan

below correct link

http://www.freescale.com/files/dsp/doc/data_sheet/IMX25CEC.pdf 

 i.MX25 has only Host 2 registers under 0x400.

Also please check Table 4-18. i.MX25 Detailed Pin Muxing

i.MX25 Reference Manual

http://www.freescale.com/files/dsp/doc/ref_manual/IMX25RM.pdf

Best regards
igor

[sayan]

Hi igor,

Thanks. 

Do you mean to say that Host2 under 0x0400 is the only Host core available in iMX257? There is no mention of 0x0400 offset in the reference manual. There is only mention of 0x0200 for Host1. I am confused.

Regards,

Sayan