i.MX25 SDIO

[KatsumiKaneko]

Hello.

I am developing the SDIO driver of i.MX257.
It is using eSDHC2.

There are two questions.

Question 1:
Teach the way of controlling the clock of the SD bus by the SDCLKEN bit of SystemControlRegister.
To want to be realized is to make the inside of the 1 bit mode stop the clock of the SD bus and to accept SDIO interruption.
It sets PEREN, HCKEN, IPGEN of SystemControlRegister to 1.
SION of the following register is set.
・IOMUXC_SW_MUX_CTL_PAD_SD1_CMD
・IOMUXC_SW_MUX_CTL_PAD_SD1_CLK
・IOMUXC_SW_MUX_CTL_PAD_CSI_D6
・IOMUXC_SW_MUX_CTL_PAD_CSI_D7

Question 2:
It sometimes becomes 0x00000000 when reading InterruptStatusRegister by the SD interruption handler.
What is thought of ?

[jimmychan]

I think you need to enable the esdhc2 clock first.

For more details, please read the i.MX25 reference manual. Chapter 15.3.3.4 Clock Gating Control Register 0 (CGCR0).

AHB Clock Gating[6]  ---  hclk_esdhc2

[KatsumiKaneko]

Thanking you.

Set to ClockGatingControlRegister0 to use eSDHC2.

Besides, what is thought of?

[jimmychan]

Please check the IOMUX. As you mentioned you will use eSDHC2, but your IOMUX setting is for eSDHC1.

[yuhe-r64908]

Hi Jimmychan,

For  Question 1,  Could you please refer to the following,

https://community.freescale.com/thread/315257

It seems that the SDCLKEN bit doesn't exist in i.MX25.

For Question 2,   the customer found that although  the value of  Interrupt Status Register (IRQSTAT) is 0x00000000, the inturrpt handler is called.  Could you please help  the problem ?

Best Regards,

Yu

[jimmychan]

For the Q2, could you tell me more details ? what interrupt is called? which bit you expected to be 1 in IRQSTAT?

[yuhe-r64908]

Hi Jimmychan,

The customer has been waiting for your solution.  Could you please help it ASAP ?

Thanks,

Yu

[jimmychan]

According to the Reference manual,

" In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, which may introducing some delay between the interrupt signal from the SDIO card and the interrupt to the host system.

Writing 1 to this bit clears it, but if the interrupt factor from the SDIO card is not cleared then the bit is immediately set again.

When CINT has been set to 1, it is the host driver’s responsibility to clear the card interrupt signal enable bit in the interrupt signal enable register, so that the eSDHC stops driving the interrupt while it is being serviced. After the card interrupt service is completed, and the interrupt factors in the SDIO card have been reset, then the host driver can write 1 to clear this bit and set the card interrupt signal enable to 1. This causes the eSDHC to restart sampling the interrupt signal. "

In you ISR, have you clear the "card interrupt signal enable bit"?

so the eSDHC stops driving the interrupt while it is being serviced.

[yuhe-r64908]

Hi Jimmychan,

Could you please check and help with it ?

Thanks,

Yu

[jimmychan]

Hi yuhe,

I don't have any new idea for this issue. I will try to ask an expert for help this.

[yuhe-r64908]

Hi Jimmychan,

Do you have any update to this issue ?    If needed, could you escalate the issue to R&D ? since the customer has been waiting for the solution.

Thanks,

Yu

[jimmychan]

Hi Yu,

I had escalated this issue to the expert team. I will try to ask them for help again to speed up the process.

[yuhe-r64908]

Hi Jimmychan,

    Any progress on the issue ?  Is a CT ticket assigned ?

  Thanks,

  Yu

[jimmychan]

sorry, I cannot create CT ticket. May need help from karinavalencia

[karina_valencia · Accepted solution]

Re: i.MX25 SDIO

DongAisheng Mar 13, 2014 2:20 AM (in response to jimmychan)

There's an errata ENGcm09399 eSDHCv2: eSDH C misses SDIO interrupt wh en CINT is disabled.

http://cache.freescale.com/files/dsp/doc/errata/MCIMX51CE.pdf

Customer's issue is a bit different from the errata description since they did not miss the interrupt but not set in interrupt status register.

I wonder did customer enable WECINT bit in protocol control register(0x28)?

Anyway, you can ask if customer's code include this errata fix?

If not please try it. It may helps.

Reference code:

static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)

{

        struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

        struct pltfm_imx_data *imx_data = pltfm_host->priv;

        u32 data;

        if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {

                if (val & SDHCI_INT_CARD_INT) {

                        /*

                         * Clear and then set D3CD bit to avoid missing the

                         * card interrupt.  This is a eSDHC controller problem

                         * so we need to apply the following workaround: clear

                         * and set D3CD bit will make eSDHC re-sample the card

                         * interrupt. In case a card interrupt was lost,

                         * re-sample it by the following steps.

                         */

                        data = readl(host->ioaddr + SDHCI_HOST_CONTROL);

                        data &= ~ESDHC_CTRL_D3CD;

                        writel(data, host->ioaddr + SDHCI_HOST_CONTROL);

                        data |= ESDHC_CTRL_D3CD;

                        writel(data, host->ioaddr + SDHCI_HOST_CONTROL);

                }

        }

.......

}

/message/387631?et=watches.email.thread

[yuhe-r64908]

Hi Jimmychan,

Thanks for your reply.

Hope the issue can be solved ASAP.

Best Regards,

Yu

[KatsumiKaneko]

Thanking you.

> In you ISR, have you clear the "card interrupt signal enable bit"?

Yes.
It clears the CINTIEN bit of Interrupt Signal Enable Register and CINTSEN bit of Interrupt Status Enable Register.

The processing is as the following.

1:The card interrupt occurrence.
2:In ISR clears the CINTIEN bit of Interrupt Signal Enable Register and CINTSEN bit of Interrupt Status Enable Register.
3:Writes interrupt factor clear in the SDIO card using CMD52.
4:Confirms interrupt clearance in the SDIO card using CMD52.
5:Reads data using CMD53.(data size is 1.5Kbytes)
6:Sets the CINTIEN bit of Interrupt Signal Enable Register and CINTSEN bit of Interrupt Status Enable Register.
7:The card interrupt occurrence.(Interrupt Status Register is 0x00000000)

It seems that it occurs when the DAT1 signal becomes LOW before the 6th processing.
When doing the 6th processing between the 4th and the 5th, the frequency falls.

Best Regards,
Kaneko

[KatsumiKaneko]

Thanking you.

It is as the following in the details.

・The interruption is 8th of the interrupt vector (eSDHC2).
・It occurs by the communication of CMD53.
・The communication of CMD53 has ended.

・It is not each time but the occurring frequency is high.
・It expects Card interrupt but Interrupt Status Register (IRQSTAT) is 0x00000000.

It attaches the screen shot of the occurrence time.
The tool is EWARM.

[yuhe-r64908]

Hi Kaneko-san,

Could you please check Jimmychan's comments and give the feedback ?

Thanks,

Yu

[KatsumiKaneko]

Thanking you.

Sorry, that the reply is slow.

It stopped the setting of IOMUXC_SW_MUX_CTL_PAD_SD1_CMD and IOMUXC_SW_MUX_CTL_PAD_SD1_CLK.
However, the operation didn't change.

It is using ATL2 mode in IOMUXC_SW_MUX_CTL_PAD_CSI_D6.
It is CMD of eSDHC2.

It is using ALT2 mode in IOMUXC_SW_MUX_CTL_PAD_CSI_D7.
It is CLK of eSDHC2.

Is there a problem in this setting?

[yuhe-r64908]

Hi Kaneko-san,

For Q2 ,  Could you please give the detailed info to Jimmychan ?

what interrupt is called? which bit you expected to be 1 in IRQSTAT?

Best Regards,

Yu