i.MX RT1170 - eDMA questions

[tzan]

Hi all, I've been using MIMXRT1170-EVK board and trying to compare the performance of eDMA module with to software memcpy function, when there's a memory to memory transfer.

To do so, I'm trying to configure eDMA in different ways but I got some errors which are not so clear for me.

buf and buff_burst are this struct:

struct dmaTest_Cluster_v_S {
uint32_t cmd;
uint32_t amount;
uint32_t dma_measure;
uint32_t sw_measure;
uint32_t count;
uint32_t source[2048];
uint32_t target[2048];
};

For both tests amount is equal to 2048.

1)  First test: SSIZE and DSIZE are configured as 32 bit mode. Here is my code:

src=&buff->source[0];
trg = &buff->target[0];
len = buff->amount;

DMA0->CR = (0 | DMA_CR_GRP0PRI(1));
DMA0->EEI = 0;
DMA0->SERQ = 0;

// TCD initialization
DMA0->TCD[0].SADDR = (uint32_t)src;
DMA0->TCD[0].SOFF = 4;
DMA0->TCD[0].DADDR = (uint32_t)trg;
DMA0->TCD[0].DOFF = 4;
DMA0->TCD[0].ATTR = (0
| DMA_ATTR_SMOD( 0 )
| DMA_ATTR_SSIZE( 2 ) // 2: 32 bit
| DMA_ATTR_DMOD( 0 )
| DMA_ATTR_DSIZE( 2 ) // 2: 32 bit
);
DMA0->TCD[0].NBYTES_MLNO = len;

DMA0->TCD[0].BITER_ELINKNO = 1;
DMA0->TCD[0].CITER_ELINKNO = 1;

DMA0->TCD[0].SLAST = 0;
DMA0->TCD[0].DLAST_SGA = 0;

__enable_irq();
buff->count = 0;
uint32_t measure_marker = GPT_GetCurrentTimerCount(EXAMPLE_GPT);
DMA0->TCD[0].CSR = ( 0
| DMA_CSR_BWC( 0 )
| DMA_CSR_MAJORLINKCH( 0 )
| DMA_CSR_MAJORELINK( 0 )
| DMA_CSR_ESG( 0 )
| DMA_CSR_DREQ( 0 )
| DMA_CSR_INTHALF( 0 )
| DMA_CSR_INTMAJOR( 0 )
| DMA_CSR_START( 1 )
);
while (!(DMA0->TCD[0].CSR & DMA_CSR_DONE_MASK)) buff->count++;
__disable_irq();
buff->dma_measure = GPT_GetCurrentTimerCount(EXAMPLE_GPT) - measure_marker;
__enable_irq();

Result: the src buffer is then copied to trg buffer but I got en error in the ES register, NCE bit is 1. Why? 

NBYTES is multiple of SSIZE/DSIZE (2048 and 32bit respectively), CITER is 1, CITER = BITER = 1.

2) Second test: in this test I set SSIZE and DSIZE in burst mode (5), in order to evaluate this functionality. Here is my code, then:

src=&buff_burst->source[0];
trg = &buff_burst->target[0];
len = buff_burst->amount;

DMA0->CR = (0 | DMA_CR_GRP0PRI(1)); 
DMA0->EEI = 0;
DMA0->SERQ = 0;

// TCD initialization
DMA0->TCD[0].SADDR = (uint32_t)src;
DMA0->TCD[0].SOFF = 32; // 8 bytes * 4 beats?
DMA0->TCD[0].DADDR = (uint32_t)trg;
DMA0->TCD[0].DOFF = 32; // 8 bytes * 4 beats?
DMA0->TCD[0].ATTR = (0
| DMA_ATTR_SMOD( 0 )
| DMA_ATTR_SSIZE( 5 ) // 2: 32 bit - 3: 64 bit - 5: 32-byte burst (4 beats of 64 bits)
| DMA_ATTR_DMOD( 0 )
| DMA_ATTR_DSIZE( 5 )
);
DMA0->TCD[0].NBYTES_MLNO = len;

DMA0->TCD[0].BITER_ELINKNO = 1;
DMA0->TCD[0].CITER_ELINKNO = 1;

DMA0->TCD[0].SLAST = 0;
DMA0->TCD[0].DLAST_SGA = 0;

//DMA0->DCHPRI0 = 0;

//interrupt_getNdisable( &itrp );
__enable_irq();
buff_burst->count = 0;
// uint32_t measure_marker = talosTick_get_timestamp_core();
uint32_t measure_marker = GPT_GetCurrentTimerCount(EXAMPLE_GPT);
DMA0->TCD[0].CSR = ( 0
| DMA_CSR_BWC( 0 )
| DMA_CSR_MAJORLINKCH( 0 )
| DMA_CSR_MAJORELINK( 0 )
| DMA_CSR_ESG( 0 )
| DMA_CSR_DREQ( 0 )
| DMA_CSR_INTHALF( 0 )
| DMA_CSR_INTMAJOR( 0 )
| DMA_CSR_START( 1 )
);
while (!(DMA0->TCD[0].CSR & DMA_CSR_DONE_MASK)) buff_burst->count++;
__disable_irq();
//buff_burst->dma_measure = talosTick_get_timestamp_core() - measure_marker - talosTick_timestamp_core_compensation;
buff_burst->dma_measure = GPT_GetCurrentTimerCount(EXAMPLE_GPT) - measure_marker;
__enable_irq();

Result: in this case, bytes transfer is not done (trg buffer is still filled by 0) and I got DAE and SAE bits to 1 in the ES register. 

From Reference Manual, SAE or DAE is set to 1 when "The most-recently recorded error was a configuration error detected in the TCDn_SADDR/TCDn_DADDR field. TCDn_SADDR/TCDn_DADDR is inconsistent with TCDn_ATTR[SSIZE/DSIZE]."

DMA0->TCD[0].SADDR and DMA0->TCD[0].DADDR are set to src and trg address which are SDK_ALIGNs. 

Would you mind address me to find the reason of these errors?

Many thanks!

T.

[Hui_Ma]

Hi,

First of all, sorry for the later reply.

We recommend customer to use MCUXpresso SDK software package for RT1170 product, which provides eDMA driver and related examples (including memory to memory copy).

RT1170's eDMA IP is original from Kinetis product platform, I searched below eDMA training materials for your reference.

Wish it helps.

eDMA for Kinetis K series MCUs

Example code on how to use DMA in Kinetis® K60