i.MX 8M Plus - external eMMC 5.1 connection

[Abishek_Devan]

Hi Team,

Currently we are working on one of the projects which connect i.MX 8M plus processor connected to external eMMC 5.1. We are planning to improve performance, and we are having some queries,

1. In reference manual the SW_PAD_CTL_PAD_SD1_CLK SW PAD Control Register (3033_02ECh), field 6 (bit 7 - Pull Up / Down Config. Field), if we are changing this field whether it will impact the reference clock to the eMMC 5.1 and it will impact in IP level also?

2. Do you have any uSDHC controller details documents? we are seeing high level block diagram in datasheet, but it has limited details.

Thanks in advance.

Regards,

Abishek

[Rita_Wang]

Do not have effect, for the usdhc1 you using you can set the same as the usdhc3:

MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190

[Rita_Wang]

[Rita_Wang]

Can the emmc work well ? How about your design for the emmc, are you connect to USDHC1 or USDHC3?

[Abishek_Devan]

Hi Rita,

Yes, eMMC is working fine. We connected our connection to the USDHC1. 

My question is if we change the SW_PAD_CTL_PAD_SD1_CLK SW PAD Control Register (3033_02ECh), field 6 (bit 7 - Pull Up / Down Config. Field), if we are changing this field whether it will impact the reference clock to the eMMC 5.1 and it will impact in IP level also?

Regards,

Abishek

[Rita_Wang]

I will help check it