how to set CCM register in driver ?

[ludovicleau-mer]

Hi,

i try to adjust several register of CCM like CSCMR1, CSCDR3 for ajust IPU1_HSP and MIPI_PIXEL clocks.

I try to get HSP > MIPI_PIXEL > 225 MHz

hsp_clk > ccm_pixel_clk/0.9 > (mipi_clk_lane frequency /(8bits*2))*Data_lane_number

in my case clock lane  = 999MHz with 4 lanes.

I see all clock definition in arch/arm/mach-imx/clk-imx6q.c but if the clock lane change it is useful to cahnge clock settings in my driver.

What is the process to set a new rate inside a driver ?

and why when i change the clok lane on mipi csi bus in the mipi_info structur does'nt change ?

thanks for your suggestion.

[igorpadykov]

Hi ludovic

please look at description of linux clock configuration

http://elinux.org/images/f/f0/Elce11_hauer.pdf

http://schedule2012.rmll.info/IMG/pdf/LSM2012_ArmKernelConsolidation_Petazzoni.pdf

Some documents for MIPI camera debug:

https://community.freescale.com/docs/DOC-94312

https://community.freescale.com/message/328301#328301

Best regards

igor

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[ludovicleau-mer]

Hi igorpadykov,

i have already read the document on MIPI debug and the thread (some experinece when enable mipi camera ). I am in the state C "check the clock settings" of this last document.

My camera have several test mode with different clock lane frequency. with two first clock (208 and 312MHz) i get the correct image. It is a fixed image with color bar.

for 416 and 499 MHz the camera doesn't work. I suspect a frequency problem.

For testing i modify clock in file clk-imx6q.c.

About clock managment :

I would get clock in my driver with clk_get(struct device *dev, const char *id); but by example for the hsp_clk (i think is ipu1 clock) i don't understand to wich device the clock is attached for get it ? I thank that is a system clock and i try clk_get(NULL, "ipu1") but it doesn't work.

About image :

i have a camera mode that use a 499MHz lanes frequency so (mipi_clk_lane / (8bit *2))*4 lanes =  249. The mipi  pixel clck is connect to emi_sel clock (396MHz)

So i have ccm_pixel_clk (396) > 249. I change the CSCDR3[IPU1_HSP_PODF] divider to set divide by one. And the ipu clock is 528Mhz (> ccm_pixel_clk)

But the result is ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0

What is the good way to debug my process or set the correct frequency to ipu and mipi_pixel_clk ?

[kristofferglemb]

Hi Ludovic,

Did you get this sorted out? I'm also interested in the answer to your question! I get the same error as you "ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0" and I'm using 400 MHz MIPI lane frequency. I suspect some kind of IPU clock issue as well.

I'm not sure which clocks that need to be set properly to work at that lane frequency. You refer to "mipi pixel clk", is it the same as ccm_pixel_clk? What are those clocks called in clk-imx6q.c ? Could you show me how you set IPU1 clock to 528 MHz?

/Kristoffer