how to change DDR clock of i.mx6

[Tony_Luo]

Hi all, the DDR clock of i.mx6 is 528MHz on boot time, but I want to change it to lower(may be 400MHz).

I read the Datasheet and found the below introduction:

"

18.2.1.5.3 PLL clock change

If software wants to change pll clock output of a specific pll, or if software wants to stop

a specific pll, then software needs first to move all the clocks generated from this pll to

another pll which is not changed.

This should be done via the glitch less mux's for the clocks which cant be stopped (core

and bus clocks). Procedure of PLL clock change is described in anatop module spec.

"

But I can't found the "anatop module spec".

By the way, in i.mx5,the clock is configure int the file of "lowlevel_init.S" by the macro of "init_clock" & "setup_pll pll, freq",

But in i.mx6,the macro of "setup_pll pll, freq" is empty and "PLL1, PLL2, and PLL3 are configured by ROM", so I have no idea of how to change DDR clock of i.mx6.

If anyone can help me please?

[sheik]

Hi,

I am trying to calibrate imx6ul processor which is having MT41J128M16 DDR3 SDRAM, I would like to calibrate the DDR below 396MHZ. I have updated the calibration sheet with 300MHZ and tried to calibrate.

Calibration was successful but device still runs in 396 MHZ. Will imx6ul work below 396MHZ DDR clock frequency?

I have updated all the Write leveling, DQS Gating, Read and write calibration register values in my .cfg file, device got booted successfully but it still runs in 396MHZ frequency. 

Could you please let me know where else I have update to make the device runs in 297MHZ clock frequency.

I have attached my calibration sheet and DDR calibration log here.

Kindly provide your inputs on the same. Please do let me know if I am missing out on anything

Thanks,

Sheik Ajith

[sheik]

Hi,

I am trying to calibrate imx6ul processor which is having MT41J128M16 DDR3 SDRAM, I would like to calibrate the DDR below 396MHZ. I have updated the calibration sheet with 300MHZ and tried to calibrate.

Calibration was successful but device still runs in 396 MHZ. Will imx6ul work below 396MHZ DDR clock frequency?

I have updated all the Write leveling, DQS Gating, Read and write calibration register values in my .cfg file, device got booted successfully but it still runs in 396MHZ frequency. 

Could you please let me know where else I have update to make the device runs in 297MHZ clock frequency.

I have attached my calibration sheet and DDR calibration log here.

Kindly provide your inputs on the same. Please do let me know if I am missing out on anything

Thanks,

Sheik Ajith

[sheik]

Hi,

I am trying to calibrate imx6ul processor which is having MT41J128M16 DDR3 SDRAM, I would like to calibrate the DDR below 396MHZ. I have updated the calibration sheet with 300MHZ and tried to calibrate.

Calibration was successful but device still runs in 396 MHZ. Will imx6ul work below 396MHZ DDR clock frequency?

I have updated all the Write leveling, DQS Gating, Read and write calibration register values in my .cfg file, device got booted successfully but it still runs in 396MHZ frequency. 

Could you please let me know where else I have update to make the device runs in 297MHZ clock frequency.

I have attached my calibration sheet and DDR calibration log here.

Kindly provide your inputs on the same. Please do let me know if I am missing out on anything

Thanks,

Sheik Ajith

[Sasamy]

Hi AnsonHuang.

Slowing the DDR3 clock rate down to 396MHz  it's not as easy as it seems.

1 ERR006282

ROM code uses nonreset PFDs to generate clocks, which may

lead to random boot failures

2 i.mx6q Linux kernel is hardcoded to ddr3 528M

linux-2.6-imx.git - Freescale i.MX Linux Tree

[AnsonHuang]

Hi, Alex

     ERR006282 is not impacting slowing down DDR3 clock rate to 396MHz, as long as uboot can boot up from SD, there is no PFD issue. For the hardcode of ddr3 to 528M, it is only for busfreq, you can disable busfreq if it is not useful for you. If you still want to use busfreq, then it needs some modification to make the highest setpoint as 396MHz, we ever support that, you can refer to i.MX6DL's code path in busfreq, it is 396MHz.

[Sasamy]

Hi Yongcai Huang, Thanks for your answer.

1 You are right,but it is necessary to disable gate/ungate 528_PFD2 for i.mx6q in u-booot

uboot-imx.git - Freescale i.MX u-boot Tree

2 I will be grateful for your advice - how to disable bus_freq correctly, enough to simply disable it in Makefile ?

[AnsonHuang]

Hi, Alex

     1. You should skip the reset of 528_PFD2 if you boot up with DDR3 running at 396M, refer to i.MX6DL's code patch;

     2. To disable busfreq, you can just comment out the "imx6q_add_busfreq" in your board file, such as in arch/arm/mach-mx6/board-mx6q_sabresd.c . Or just set bus_freq_scaling_is_active to 0 in arch/arm/mach-mx6/bus_freq.c's busfreq_init routine. Either way is OK.

[Sasamy]

Hi AnsonHuang

Thank you very much - you really helped.