how does the DI interact with DC?

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how does the DI interact with DC?

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senixsenix
Contributor I

How does the Di trigger Dc based on some of the DI‘timers,when hsysnc vsync happened?

Look into the driver:

int32_t ipu_init_sync_panel(...)

{

...

/* Setup internal HSYNC waveform */

  _ipu_di_sync_config(ipu, disp, 1, h_total - 1, DI_SYNC_CLK,

  0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,

  DI_SYNC_NONE, 0, 0);

//what’s the  internal HSYNC?

...

/* Setup active data waveform to sync with DC */

  _ipu_di_sync_config(ipu, disp, 4, 0, DI_SYNC_HSYNC,

     v_sync_width + v_start_width, DI_SYNC_HSYNC, height,

     DI_SYNC_VSYNC, 0, DI_SYNC_NONE,

     DI_SYNC_NONE, 0, 0);

  _ipu_di_sync_config(ipu, disp, 5, 0, DI_SYNC_CLK,

     h_sync_width + h_start_width, DI_SYNC_CLK,

     width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,0);

//Timer 4/5 is used to sync with DC? but,how?  trigger DC to send data to the Di?

...

}

It seems no any explanation in the RM.

Can someboy provide the doc.


and how does the Di'pin connect with LDB,HDMI? any picture?

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qiang_li-mpu_se
NXP Employee
NXP Employee

  _ipu_di_sync_config(ipu, disp, 1, h_total - 1, DI_SYNC_CLK,

     0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,

     DI_SYNC_NONE, 0, 0);

[Qiang]: for this code, it means the DI counter 1 was based on DI_SYNC_CLK clock (counter 0, Pixel clock), it will trigger every h_total pixel clocks, so it is a HSYNC signal, but no output from DI_PIN01.

  _ipu_di_sync_config(ipu, disp, DI_SYNC_HSYNC, h_total - 1,

        DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK,

        0, DI_SYNC_NONE, 1, DI_SYNC_NONE,

        DI_SYNC_CLK, 0, h_sync_width * 2);

[Qiang]: for this code, it means DI counter 2 was based on DI_SYNC_CLK clock (counter 0, Pixel clock), it will trigger every h_total pixel clocks, so it is also HSYNC signal, but different with counter 1, it had set trigger_src and up/down, that means it will output timing signal from DI_PIN02. And the trigger clock source is counter 0 (pixel clock), so this is the real HSYNC to external display.

  _ipu_di_sync_config(ipu, disp, DI_SYNC_VSYNC, v_total - 1,

        DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0,

        DI_SYNC_NONE, 1, DI_SYNC_NONE,

        DI_SYNC_INT_HSYNC, 0, v_sync_width * 2);

[Qiang] counter 3, the real VSYNC, it's clock source is internal HSYNC, counter 1.

  _ipu_di_sync_config(ipu, disp, 4, 0, DI_SYNC_HSYNC,

        v_sync_width + v_start_width, DI_SYNC_HSYNC, height,

        DI_SYNC_VSYNC, 0, DI_SYNC_NONE,

        DI_SYNC_NONE, 0, 0);

[Qiang] this counter is the active frame counter, it will skip the vsync blanking lines, and the counter will restart when each VSYNC event triggers.

  _ipu_di_sync_config(ipu, disp, 5, 0, DI_SYNC_CLK,

        h_sync_width + h_start_width, DI_SYNC_CLK,

        width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,

        0);

[Qiang] this counter is the active line counter, it will skip the hsync blanking columes, its clock source is the pixel clock.

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