ethernet phy-reset using GPIO pin

[Eduardo-S-Oliveira]

I'm trying to use the external ethernet but I can't configure phy-reset. As a workaround, I've implemented a shell script to toggle the phy-reset and reboot the imx93, in this condition, the ethernet is working. When I try to configure the same gpio (GPIO2_IO27) as the phy-reset in the device tree, it's not working. Measuring with an oscilloscope, I didn't see the pin toggle. What I'm doing wrong? This a part of my device tree

fecgrp {

fsl,pins = <0xf8 0x2a8 0x00 0x00 0x00 0x57e 0xfc 0x2ac 0x00 0x00 0x00 0x57e 0x100 0x2b0 0x00 0x00 0x00 0x57e 0x104 0x2b4 0x00 0x00 0x00 0x57e 0xf4 0x2a4 0x00 0x00 0x00 0x58e 0xf0 0x2a0 0x00 0x00 0x00 0x57e 0xe4 0x294 0x00 0x00 0x00 0x57e 0xe0 0x290 0x00 0x00 0x00 0x57e 0xdc 0x28c 0x00 0x00 0x00 0x57e 0xd8 0x288 0x00 0x00 0x00 0x57e 0xec 0x29c 0x00 0x00 0x00 0x58e 0xe8 0x298 0x00 0x00 0x00 0x57e 0x7c 0x22c 0x00 0x00 0x00 0x91e>;

phandle = <0x3f>;

};

ethernet@42890000 {

    compatible = "fsl,imx93-fec", "fsl,imx8mq-fec";

    reg = <0x42890000 0x10000>;

    interrupts = <0x00 0xb3 0x04>, <0x00 0xb4 0x04>, <0x00 0xb5 0x04>, <0x00 0xb6 0x04>;

    clocks = <0x07 0xb6>, <0x07 0xb6>, <0x07 0x5d>, <0x07 0x5f>, <0x07 0x60>;

    clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out";

    status = "okay";

    pinctrl-names = "default";

    pinctrl-0 = <0x3f>;

    phy-mode = "rgmii-id";

    phy-handle = <0x40>;

};

ethernet@428a0000 {

compatible = "nxp,imx93-dwmac-eqos\0snps,dwmac-5.10a";

reg = <0x428a0000 0x10000>;

interrupts = <0x00 0xb8 0x04 0x00 0xb7 0x04>;

interrupt-names = "macirq\0eth_wake_irq";

clocks = <0x07 0xb7 0x07 0xb7 0x07 0x5e 0x07 0x5c 0x07 0xb7>;

clock-names = "stmmaceth\0pclk\0ptp_ref\0tx\0mem";

assigned-clocks = <0x07 0x5e 0x07 0x5c>;

assigned-clock-parents = <0x07 0x06 0x07 0x04>;

assigned-clock-rates = <0x5f5e100 0xee6b280>;

intf_mode = <0x27 0x28>;

snps,clk-csr = <0x05>;

nvmem-cells = <0x42>;

nvmem-cell-names = "mac-address";

status = "okay";

pinctrl-names = "default";

pinctrl-0 = <0x43>;

phy-mode = "rgmii";

phy-handle = <0x44>;

phandle = <0xb3>;

mdio {

compatible = "snps,dwmac-mdio";

#address-cells = <0x01>;

#size-cells = <0x00>;

clock-frequency = <0xf4240>;

ethernet-phy@0 {

compatible = "ethernet-phy-ieee802.3-c22";

reg = <0x00>;

eee-broken-1000t;

reset-gpios = <0x13 0x07 0x01>;

reset-assert-us = <0x2710>;

reset-deassert-us = <0x186a0>;

mxl-8611x,led0_cfg = <0x2600>;

mxl-8611x,led1_cfg = <0x70>;

phandle = <0x44>;

};

ethernet-phy@5 {

compatible = "ethernet-phy-ieee802.3-c22";

reg = <0x05>;

reset-gpios = <0x15 0x1b 0x01>;

reset-assert-us = <0x2710>;

reset-deassert-us = <0x13880>;

phandle = <0x40>;

};

};

};

[Eduardo-S-Oliveira]

Hi, @Chavira,

I'm using a VAR-SOM-MX93 from Variscite. I don't know exactly what BSP version is running.
I'm attaching the device tree; it's a customization from the Variscite original device tree.

[Chavira]

Hi @Eduardo-S-Oliveira,

After reviewing your device tree, the configuration itself looks correct; however, the PHY reset GPIO is currently configured as active‑high.

In the node ethernet-phy@5, you have:

reset-gpios = <0x15 0x1b 0x00>;

The third value (0x00) indicates GPIO_ACTIVE_HIGH, meaning the reset signal is asserted when the GPIO is driven high.

If your hardware expects the PHY reset to be active‑low, you should change this line to:

reset-gpios = <0x15 0x1b 0x01>;

This sets the reset GPIO to GPIO_ACTIVE_LOW, so the reset is asserted when the signal is driven low.

What reset behavior are you expecting on the PHY side?

Best Regards,
Chavira

[Chavira]

Hi @Eduardo-S-Oliveira,

Thank you for contacting NXP Support!

Could you please provide the following information so we can better analyze the issue?

Which BSP version are you working with?
Would you be able to share your device tree file?

This information will help us reproduce the setup and investigate the problem more effectively.

Best regards,
Chavira