eMMC Partition error during power up

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eMMC Partition error during power up

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umasundaram
Contributor II

      We are using a System-On Module(SOM) with iMX6(Solo) processor and Micron eMMC(Part No:MTFC4GMDEA-4M IT). As a design requirement, we have to read the FAT32 partition in eMMC first, before reading the kernel image(from boot partition).

   Sometimes, on trying to read the FAT32 partition in u-boot,the partition is reported missing and is not able to detect any of the eMMC partitions and the device stops at u-boot.We skipped reading the FAT partition and it got stuck while reading the kernel from boot partition.This issue can be easily reproduced when the device(to which SOM is connected),is powered OFF and turned ON quickly (within a difference of about 2 seconds).

    We probed the Core and IO power domains (VCC and VCCQ) and reset of the eMMC, but both the power rails were stable and the device was out of reset,when the corruption occurs.

   On checking the eMMC read code, to identify the failure, we could see a timeout error.

Below is the time-out error log for reference.

mmc_bread() 411:Called

CMD_SEND:17

                ARG                      0x00000000

                FLAG                     0

esdhc_send_cmd() 279: err -19

esdhc_send_cmd() 280: xfertyp 0x113a0018

                MMC_RSP_R1,5,6,7         0x57995F0A

                Return ret -19

mmc_read_blocks() 384: ERROR

** Can't read from device 0 **

** Unable to use mmc 0:9 for fatload **

   As it was a time-out error, we tried reducing the SD clock from 52 MHz to 26MHz in u-boot  and in kernel,we are again configuring the SD clock to 52MHz. We are not able to reproduce the eMMC corruption issue with SD clock at 26MHz (so far) in u-boot.

         Can you please let us know why the time-out error occurs when the device is turned OFF and ON quickly.Is reducing the SD_Clock is actually a solution.Also if SD_Clock needs to be reduced at u-boot, do we need to lower the clock in kernel too.

   Please let us know the cause for the eMMC corruption issue.Your hekp is highly appreciated.

Thanks,

Uma

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3,154 Views
umasundaram
Contributor II

Hi Igor,

   We moved spread spectrum enabling code before DDR init for our board. We did this by building single bootloader (instead of two stages : SPL and u-boot.bin) 'u-boot.imx' binary in plugin mode. In that Spread Spectrum and DDR init is done in plugin code.
   We tried both 30MHz and 15MHz frequency range in spread spectrum configuration. But still we are facing issue in reading partition table and reading file from partition of eMMC.
   We confirmed that this issue (reading partition table and reading file from partition of eMMC) is NOT happening when Spread Spectrum is disabled.
Could you please let us know why there is an eMMC boot up issue,if we enable the spread spectrum feature as per NXP suggested in document 'spread spectrum.docx'.

Please find the document attached for your reference.Also please find the reference NXP forum link for the document.

enable the spread spectrum 

Thanks,

Uma.

   

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3,154 Views
umasundaram
Contributor II

Hi Igor,

   

Please find below the details of spread spectrum enabling in our u-boot code,for your reference. 

-----------------------------------------------------------------------------------------------------

   In our product, the bootloader is split into two : SPL and u-boot.bin.Both SPL and u-boot.bin are programmed into eMMC chip memory.

 SPL code, initializes RAM memory using IVT table and DCD, then loads u-boot.bin from eMMC to RAM memory

 u-boot.bin code, initializes other peripherals and enables spread spectrum.

The spread spectrum is enabled after enabling IPU display and before MMC init.

The spread spectrum is enabled with 30MHz range and 120 KHz frequency step by programming following registers

[0x20C8060] = 0x190

[0x20C8040] = 0x1F48002

 

Find below boot sequence of our product

  1. Power on. RBL finds valid boot binary (i.e SPL code) in eMMC, then copies SPL from eMMC to internal SRAM memory
  2. SPL is running. This SPL binary does following:
    1. It is having IVT table and DCD for initializing DDR memory
    2. Initializing debug serial port
    3. Initializing SD/MMC interface
    4. Reading u-boot env variables from eMMC memory
    5. Copying u-boot.bin binary from eMMC to DDR memory
    6. Run u-boot.bin from DDR memory
  3. u-boot.bin is running. This u-boot.bin does following
    1. Initialize other peripherals in order of:
      1. LEDs,
      2. UART,
      3. OTG
      4. SPI
      5. GPIOs for Power Enable/Disable of for WiFi, GPS, GSM, Audio Codec, Light Chamber, Camera, Ethernet, USB and Host Hub,
      6. LVDS display,
      7. Spread Spectrum,
      8. eMMC,
      9. GPIOs for BACK,HOME and MENU key
      10. I2C
    2. Reading u-boot env variables from eMMC memory
    3. Read micro controller firmware file from 9th Partition (type is VFAT) of eMMC chip.
    4. Program firmware to microcontroller if the firmware file read from eMMC is an updated one
    5. Read Android Boot image from eMMC. If reading is failed , change to fastboot mode for getting image over OTG.
    6. Boot android kernel

Thanks,

Uma

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igorpadykov
NXP Employee
NXP Employee

Hi Uma

 

30MHz range seems as too big for i.MX6S 400MHz ddr clock,
reasonable dithering range is 1-3%. Also Spread Spectrum configuring

one can try to move to step 2.

 

Best regards
igor

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3,154 Views
umasundaram
Contributor II

Hi,

  On debugging ,we could find that if we disable the spread spectrum feature(which is enabled as per the design requirement),the eMMC partition table error is not reproducible.

   Can you please let us know why there is an eMMC boot up issue,if we enable the spread spectrum feature.

Thanks,

Uma

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3,154 Views
igorpadykov
NXP Employee
NXP Employee

could you describe how had you managed to enable the spread spectrum feature during boot.

Best regards
igor

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3,154 Views
umasundaram
Contributor II

Hi Igor,

  Thanks for your response.We tried tweaking the pad settings(IOMUXC_SW_PAD_CTL_PAD_xx registers) for Drive strength, Slew rate and pull-up resistor values.But we are still not able  to fix the issue.

Also with the SD_CLK set at 26MHz in u-boot,we could still able to see the eMMC corruption issue.

   Can you please let us know is there any command sequence need to be followed on the eMMC read code(we use 9 eMMC partitions in our design).Is there any additional commands need to be sent, in response to time-out error for single/multi-block read.

Your help is highly appreciated.

Thanks,

Uma.

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3,154 Views
igorpadykov
NXP Employee
NXP Employee

Hi Uma

one can look at example of programming emmc with uboot (Warp7 board)
http://git.denx.de/?p=u-boot.git;a=blob;f=board/warp7/README;h=60339da543732829d4ac09f02178cb84dfa3b...

Best regards
igor

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3,154 Views
igorpadykov
NXP Employee
NXP Employee

Hi Uma

as issue appears with high frequency clock this may point to

signal integrity issues due to reflections. One can try to tweak drive strength

using (IOMUXC_SW_PAD_CTL_PAD_xx registers and check board layout

using i.MX6 System Development User’s Guide
http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf

Best regards
igor
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