change settings for Sabresd board

[niklasmolin]

Hi.

I wonder where I modify the settings (number of SPI , settings of IOMUXC etc.) for the SabreSD board (Yocto)?

I was trying to find something like board-mx6q_sabresd.c, but there is no such of file in tmp/work/imx6qsabresd-poky-linux-gnueabi/linux-imx/3........ path

When I played around with the Sabrelite board, I used board-mx6q_sabrelite.c to change my setup.

Can anyone direct me how to do the same thing for the SabreSD board?

Thanks,

Niklas

[AnsonHuang · Accepted solution]

Hi, Niklas

     We did NOT have board file now for kernel L3.10 with Yocto, you need to modify the DTS file as you listed. All those info are in dts file, for i.MX6Q, you should lookup the module you want in arch/arm/boot/dts/imx6q.dtsi, arch/arm/boot/dts/imx6qdl.dtsi and arch/arm/boot/dts/imx6qdl-sabresd.dtsi. Do all the changes you want in these files, kernel will get them. To answer your question about the pin group, there are two groups that can be set to ecspi1, KEY_COL and DISP_DAT, you can lookup the ECSPI1_MISO in IOMUXC. For ECSPI3, there is only one group. You should use the right group according to your board design.

[niklasmolin]

Hi Yongcai.

Thanks for your answer.

That was showing that I was going in the right direction.

Whats it the difference between the .dtsi and .dts files?

In the imxqdl-sabresd.dtsi file, there is an instanciation of the ecspi1:

&ecspi1 {

  fsl,spi-num-chipselects = <1>;

  cs-gpios = <&gpio4 9 0>;

  pinctrl-names = "default";

  pinctrl-0 = <&pinctrl_ecspi1_2>;

  status = "okay";

  flash: m25p80@0 {

  #address-cells = <1>;

  #size-cells = <1>;

  compatible = "st,m25p32";

  spi-max-frequency = <20000000>;

  reg = <0>;

  };

};

Is this where I should setup the chip select, and not in the pinctrl_ecspi1_1 and not in the imx6qdl.dtsi file?

How does this <&gpio4 9 0>; work? (9?  0?)

If I want to add a CS, how would that look like?

In the pinctrl setup, I noticed for the ENET_REF_CLK, it had a longer value:

MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8

The IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK doesn't have anytthing for bit 17-31 in the manual (Reserved). I assume this higher part of the value goes to a different register?

Best regards,

Niklas

[AnsonHuang]

hi, Niklas

     See below inline:

Thanks for your answer.

That was showing that I was going in the right direction.

Whats it the difference between the .dtsi and .dts files?

In the imxqdl-sabresd.dtsi file, there is an instanciation of the ecspi1:

&ecspi1 {

  fsl,spi-num-chipselects = <1>;

  cs-gpios = <&gpio4 9 0>;

  pinctrl-names = "default";

  pinctrl-0 = <&pinctrl_ecspi1_2>;

  status = "okay";

  flash: m25p80@0 {

  #address-cells = <1>;

  #size-cells = <1>;

  compatible = "st,m25p32";

  spi-max-frequency = <20000000>;

  reg = <0>;

  };

};

Is this where I should setup the chip select, and not in the pinctrl_ecspi1_1 and not in the imx6qdl.dtsi file?

How does this <&gpio4 9 0>; work? (9?  0?)

If I want to add a CS, how would that look like?

[Anson] Please read the binding doc in Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt, <&gpio4 9 0> means gpio4_9, it is KEY_ROW1 in our SabreSD board wotked as CSPI1_CS0. If you want to add a CS, you should know which pin, and this pin can be muxed to gpio?_?, then add one line as below, you can refer to other platfroms in dts folder.

arch/arm/boot/dts/imx53-evk.dts:

cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;

In the pinctrl setup, I noticed for the ENET_REF_CLK, it had a longer value:

MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8

The IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK doesn't have anytthing for bit 17-31 in the manual (Reserved). I assume this higher part of the value goes to a different register?

[Anson] No, you should read the DOC Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt, the bit 30 meas this pin should set to input mode, SION in IOMUXC.

Best regards,

Niklas

[niklasmolin]

I found some .dts .dtsi files.

Is this where the modifications should be done?

In one file I found:

	ecspi1 {
		pinctrl_ecspi1_1: ecspi1grp-1 {
			fsl,pins = <
				MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
				MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
				MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
			>;
		};

		pinctrl_ecspi1_2: ecspi1grp-2 {
			fsl,pins = <
				MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
				MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
				MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
			>;
		};
	};

What does the grp-1 and grp-2 mean in this case, since for SPI3 I only have one grp?

	ecspi3 {
		pinctrl_ecspi3_1: ecspi3grp-1 {
			fsl,pins = <
				MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
				MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
				MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
			>;
		};
	};

Thanks,

Niklas