about Internal POR

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about Internal POR

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goto11
Contributor III

Hello,Community

In the case of Internal POR, is the release timing of the reset inside the CPU when both VDD_ARM_IN and VDD_SOC_IN are supplied?
In the case of BOOT with QuadSPI (QSPI) flash, what is the delay time from the supply of both VDD_ARM_IN and VDD_SOC_IN to the start of access to flash?


Excerpt from i.MX 7Dual Applications Processor Reference Manual

6.2.5.2 Internal POR
If the external SRC_POR_B signal is not used (always held high or left unconnected), the processor defaults to the internal POR function (PMU controls generation of the POR based on the power supplies).
If the internal POR function is used, the following power supply requirements must be met:
• VDD_ARM_IN and VDD_SOC_IN may be supplied from the same source, or
• VDD_SOC_IN can be supplied before VDD_ARM_IN with a maximum delay of 1ms.

best regards

Goto

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Goto

>In the case of Internal POR, is the release timing of the reset inside the CPU when
>both VDD_ARM_IN and VDD_SOC_IN are supplied?

in general yes. However please note that "Internal POR" case was not validated
and not recommended in practice, recommended to use option with externally provided
POR.

>In the case of BOOT with QuadSPI (QSPI) flash, what is the delay time from the supply
>of both VDD_ARM_IN and VDD_SOC_IN to the start of access to flash?

Such delay is not specificed, as it depends on many factors. Please refer to below
part of Reference Manual describing reset timings.

pastedImage_1.jpg

Best regards
igor
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