Writing lpgpr via U-Boot

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Writing lpgpr via U-Boot

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sguy
Contributor III

When I try to write the LPGPR of imx6ul via U-Boot, nothing happens:

=> md.l 020cc090 4
020cc090: 00000000 00000000 00000000 00000000    ................
=> mw.l 020cc090 12345678
=> md.l 020cc090 4       
020cc090: 00000000 00000000 00000000 00000000    ................

After the first time the Linux kernel is booted on on a system, the issue disappears:

=> mw.l 020cc090 12345678
=> md.l 020cc090 4
020cc090: 12345678 00000000 00000000 00000000    xV4.............

If the VDD_SNVS_IN power is removed, the issue returns on the next power on.

Probably some kind of initialization must happen on the snvs before the register can be written.

What am I doing wrong?

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steveschefterti
Contributor III

I'm rather late to the party, but in case anyone else run into this issue:

The problem seems to be that the processor won't let you write to the SNVS GPR register when there is a power glitch detected.  That's shown in SNVS_LPSR.  You need to change the SNVS_LP Power Glitch Detector register (LPPGDR) and then clear the bit in SNVS_LPSR. That is done by Linux's SNVS RTC driver, which is why writing to GPR works after running Linux.  LPPGDR isn't described in the RM; the value I used is from the RTC driver.

Hit any key to stop autoboot:  0
=> mm.l 0x20cc064
020cc064: 00000000 ? 41736166
020cc068: 00000000 ? ^C

=> mm.l 0x20cc04c
020cc04c: 40000008 ? 8
020cc050: 00000000 ? ^C

=> mm.l 0x20cc068
020cc068: 00000000 ? 2
020cc06c: 00000000 ? ^C

=> md.l 0x20cc068 1
020cc068: 00000002

Regards,

   Steve

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sguy
Contributor III

Although those bits aren’t set, the issue exist:

=> md.l 020cc034 1
020cc034: 00000000                               ....
=> md.l 020cc000 1
020cc000: 00000000                               ....
=> md.l 020cc090 4
020cc090: 00000000 00000000 00000000 00000000    ................
=> mw.l 020cc090 12345678
=> md.l 020cc090 4
020cc090: 00000000 00000000 00000000 00000000    ................

(Line 2 shows that the LPLR, including the GPR_HL reads as zeros; line 4 shows that the HPLR, including the GPR_SL reads as zeros; lines 7-9 shows that writing to the LPGPR its content doesn't change)

What else can it be?

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igorpadykov
NXP TechSupport
NXP TechSupport

please check if CCM_CCGR5 snvs_lp clock, snvs_hp clock clocks are enabled.

Best regards
igor

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sguy
Contributor III

I believe that those clocks are enabled:

The register on 020c407c (CCM_CCGR5) content is 0xfffffffff.

Is there other thing I should check?

(I don't have access to JTAG probe)

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igorpadykov
NXP TechSupport
NXP TechSupport

what uboot version used in the case, please try

uboot-imx.git - Freescale i.MX u-boot Tree 

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Guy

when GPR_SL or GPR_HL bits are set, that register cannot be programmed.

So one can check them, description can be found in Chapter 46
Secure Non-Volatile Storage (SNVS) i.MX6UL Reference Manual

http://www.nxp.com/docs/en/reference-manual/IMX6ULRM.pdf

Best regards
igor
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sguy
Contributor III

Hi Igor.

I'm yet to overcome this issue.

Igor, are you able to reproduce the problem on your devices?

Are there any mechanisms that I am not aware of and might prevent writing the register?

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Guy

had you tried to write it using jtag.

Best regards
igor

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