Why the difference between mex reference design and Linux 5.4 pinmux for MCIMX6ULL-EVK?

[JohnKlug]

I looked at the mex file MCIMX6ULL-EVK-REV-A.mex and compared to what is in the Linux source for Ethernet, and find a difference.

For init_enet_pinsGrp I see:

MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK	0x000010B0

Looking in Linux I start with this board:

imx6ull-14x14-evk.dts 

I find:

ENET1_TX_CLK 

This has the following definition:

MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031

So is the MEX file incorrect that comes with i.MX version 8.0?

[JohnKlug]

In a related question, what is the meaning of a pinmux value of 0x40000000?  In my i.MX 6ULL Applications Processor Reference Manual, it appears that bits 17-31 are reserved.

For instance IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK  says 31-17 This field is reserved in chapter 32, page 1851 or the i.MX 6ULL Applications Processor Reference Manual.  However this bit appears to be set in Linux source code.

Here are some from imx6ul-14x14-evk.dtsi:

imx6ul-14x14-evk.dtsi: MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
imx6ul-14x14-evk.dtsi: MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
imx6ul-14x14-evk.dtsi: MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
imx6ul-14x14-evk.dtsi: MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
imx6ul-14x14-evk.dtsi: MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
imx6ul-14x14-evk.dtsi: MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0

This can be found here:

5.4.47_2.2.0 - imx6ul-14x14-evk reference design 

[igorpadykov]

Hi JohnKlug

correct is dts file:  MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031

>what is the meaning of a pinmux value of 0x40000000?

this is described in documentation:

https://source.codeaurora.org/external/imx/linux-imx/tree/Documentation/devicetree/bindings/pinctrl/...

SION(1 << 30): Software Input On Field.

sect.32.3.2 SW Loopback through SION bit  i.MX 6ULL Applications Processor Reference Manual

Best regards
igor

[JohnKlug]

So what text is selecting a mux mode?

Force the selected mux mode input path no matter of MUX_MODE functionality.
By default the input path is determined by functionality of the selected
mux mode (regular).

Does this select the mux mode?

MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1

[igorpadykov]

>In a related question, what is the meaning of a pinmux value of 0x40000000?

>In my i.MX 6ULL Applications Processor Reference Manual, it appears that bits 17-31 are reserved.

0x40000000 is linux dts convention, not Reference Manual. It is bit 4 of

IOMUXC_SW_MUX_CTL_PAD_* registers described in Chapter 30 IOMUX Controller (IOMUXC)

>what text is selecting a mux mode?.

Mentioned text "Force the selected mux mode input path"

refers to sect.30.3.2 SW Loopback through SION bit

i.MX 6ULL Applications Processor Reference Manual

Best regards
igor