Where is the documentation on the IPU Memory areas?

[elijahbrown]

In the Freescale SDK IPU driver, Display control submodule, the microcode gets written to an area starting in IPU_MEM_DC_MICROCODE_BASE_ADDR.  This winds up being 0x02780000 in the system memory map, but I can't find any documentation on this in the datasheet. 

Same thing in the display processor section, there are registers like SRM_DP_COM_CONF_SYNC which wind up being at 0x02740000 which again has no documentation.  I see mentions of an "IPUv3 Spec".  Maybe that's where this stuff is at?  Can you point us at this please?  Thanks. 

[Yuri]

Hello,

  The following thread clarifies the available for users IPU address range :

Writing to the IPU's CPMEM region

"For iMX6, IPU registers start from 0x02600000, and CPMEM is at 0x02700000.

The code defined "REGS_IPU1_BASE (0x02400000)" is based on old document, but when

access registers, it will always add offset 0x00200000. In new document, the IPU1 address had

been changed to 0x02600000. Software haven't update to this base address, there is no function

impact, because the software will always use 0x02400000 + 0x00200000 to access IPU registers."

Have a great day,
Yuri

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[elijahbrown]

Thanks, I understand the addresses but I was looking for more detail, similar to how the main IPU registers are defined in the IMX reference manual.  Documentation on the bitfields and such.  So the SDK code is the only documentation on registers like SRM_DP_COM_CONF_SYNC (IPU_MEMORY_OFFSET+0x0040000)?

[qiang_li-mpu_se · Accepted solution]

For IPU internal memory, their detail format can be found from IPU "37.4 Functional Description". You can find the detail description.

For example:

For IPU channel setting memory: 37.4.2.10 CPMEM - Channel Parameter Memory

For IPU microcode memory: 37.4.7.4 DC's Template structure

[elijahbrown]

Thank you, that's what I was looking for.