WDOG32 and NVIC_SystemReset Not Triggering System Reset at Low Core Frequency on i.MX8ULP M33

[dhruvinrajpura]

Hello,

I’m working on the i.MX8ULP EVK and using the M33 core. I’ve implemented WDOG32 with a 4-second timeout. The watchdog behaves as expected when the core is running at a high frequency (e.g., 160 MHz) — it resets the system if not refreshed within the timeout.

However, when I reduce the core clock to a lower frequency (e.g., 38.4 MHz), the watchdog still times out after the expected duration, but it does not trigger a system reset. Instead, the system just stops executing on both M-core and A-core after the timeout expires.

To further debug the issue, I also tried manually triggering a reset using:

NVIC_SystemReset();

This software-triggered reset also works at high frequency but fails to reset the system at low frequency (38.4 MHz).

Any guidance, register settings, or documentation references would be greatly appreciated.

Thanks!

[dhruvinrajpura]

Thank you for your response @Manuel_Salas.

I can confirm that I am using WDOG0, and I’m able to reproduce the issue when lowering the core frequency using below function:

BOARD_SwitchDriveMode();

After this, the CLOCK_GetFreq(kCLOCK_Cm33CorePlatClk) shows 38.4 MHz, indicating I'm running in ARBB (under-drive) mode.

1.  Is CM33_BUSCLK required to run at 24 MHz for WDOG0 reset functionality to work, or is 20 MHz (as listed in the table) acceptable?
2. If I want to use under-drive mode and retain watchdog-based system reset capability, is there a supported method to achieve      this


My product is battery-powered, so using under-drive mode is essential for power savings — but I also need the watchdog to reliably reset the system when required.

[Manuel_Salas]

Hello @dhruvinrajpura 

Yes, it should be possible according to Reference Manual, look at chapter 9.1.7 Power mode details (real-time domain):

As you can see all the necessary components to WDOG0 are available during ARBB mode, but maybe there is the possibility that uPower is gating clock of this WDOG or maybe of entire PBRIDGE0.

Please take a look to the uPower Firmware User's Guide.

Best regards,

Salas.

[Manuel_Salas]

Hello @dhruvinrajpura 

I hope you are doing very well.

As you are running in ARBB mode (under drive at 38.4 MHz), please see the Table 16. Clock frequencies from Datasheet.

That is described in that mode, some peripherals, including WDOG are deactivated or gated in under drive mode.

The only WDOG that works in this mode is the WDOG0 running at 24 MHz but in this same mode CM33_BUSCLK is at 20 MHz and CM33_SLOWCLK is at 12.5 MHz.

Also, you can check the uPower guide to see the RTD connection:

In few words, at 1.05V / 160 MHz the clocks are fully enabled, there is not forced clock gating and reset system fully clocked.

I hope this can helps to you.

Best regards,

Salas.