We would like to be able to access GPIOs owned by the M4 on the A35 (Linux) using the SRTM service/APIs. We have a demo application for SRTM which does "virtual" I2C access, and we just want to double-check if similar functionality is possible with GPIOs. If this possible, we'd also like to understand what the capabilities are with respect to this functionality (i.e. will it do interrupts, what is the latency, is there any documentation, etc).
1.-On i.MX8MM, both M4 core and A53 core can access the same module, e.g. i2c, gpio.
User needs to setup access permissions in XRDC setting.
Also, user needs to make sure that both cores should avoid access confliction, that is, both cores should not access the same module at the same time.
2.-If GPIOs are assigned to M4 only in your case, I think A53 can send msg to M4 for GPIO operations with RPMSG communication channel.
User can refer to ttyRPMSG, rpmsg ping-pong or rpmsg character device mechanism for this (User can find str echo and ping-pong examples in M4 SDK).
In all these ways, interrupt can be supported.
For interrupt latency, method 1 is definitely faster than method 2.
Hope this helps,