Using DMA from M7 target on IMX8M+

[David_Sailor]

Hi,

I'm using IMX8M+ SOC with:

• LINUX kernel on A53 using UART1 with SDMA1
• FreeRTOS on M7 using UART2 bus

I want to use a DMA on UART2, but the refManual says: 

• SDMA-1 is a general-purpose DMA engine which can be used by low speed

peripherals including UART, SPI and also others peripherals.

• SDMA-2 and SMDA-3 is used for audio interface, including SAI-1/2/3/5/6/7, SPDIF and PDM audio input.

My questions are:

• If SDMA1 is already used by LINUX four UART1, can I use SDMA1 on M7 side for UART2 ?
• SDMA2/3 are dedicated to another functions, can I use them if I don't use SAI or audio?
• I've seen that eDMA is available, but I don't see it on memory map, only SDMA are mapped (chap 2.4). Is it possible to use it for UART?

Thanks for your help

[Bio_TICFSL]

Hello,

I can address your question about using DMA with UART2.

The i.MX8M Plus has multiple SDMA controllers with specific purposes:
- SDMA-1 is the general-purpose DMA engine designed for low-speed peripherals including UART
- SDMA-2 and SDMA-3 are dedicated to audio interfaces (SAI, SPDIF, PDM)

For UART2 implementation with DMA, you should use SDMA-1. This controller is specifically intended to handle DMA operations for UART interfaces along with other low-speed peripherals like SPI.

When implementing this on the M7 core, be aware of potential resource conflicts if Linux is running on the A53 cores simultaneously. In such cases, you may need to disable SDMA1 in the Linux device tree to prevent conflicts between cores attempting to access the same DMA controller.

The UART driver in combination with SDMA1 is the appropriate configuration for your UART2 DMA implementation on the i.MX8M Plus.

Regards

[David_Sailor]

Hi,

thanks for your answer.

Linux uses UART1 with SDMA1, so if I understand your answer, I can't use SDMA1 for UART2 on M7 side.

Can I use eDMA to retrieve data from UART2 ?

Regards

[Bio_TICFSL]

Hello,

Yes, you can use eDMA to retrieve data from a UART, including UART2, on an i.MX processor by configuring the eDMA controller to trigger on a UART receive request and directing the data to a memory buffer.

regards