Thank you for your response!
Actually, I want to continuously read the data from an ADC in the kernel thread, so when I don't use the DMA and go with the PIO method, the CPU usage just goes crazy (> 70%). For SPI transactions, I wish to offload that using DMA. I have made changes in the spi-imx.c to forcefully use the dma instead of 64-byte fifo limit.
While the standard regiser read/write APIs function well with DMA, the SPI transactions fail when reading the samples, and spi_sync returns an error code.
What could be the issue? Something I have overlooked?
PS: When I perform a register read/write transaction, I also receive the DMA debug prints, confirming that DMA is functioning with register read/write.
Here's my api to read the samples
int ad4134_sample_read(struct spi_device *spi)
{
int ret;
uint32_t pad[8] = {0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff};
struct spi_transfer tr =
{
.tx_buf = pad,
.rx_buf = st.sample,
.len = 32,
.bits_per_word = 32,
};
struct spi_message m;
spi_message_init(&m);
spi_message_add_tail(&tr, &m);
spi_sync(spi,&m);
return 0;
}
