Understanding GPIO Number Calculation for GPIO2_IO00 on IMX9352 Board

[Embedded-world]

Dear Experts,

I'm working on a custom board based on the IMX9352 NPU processor. This board includes an RS485 peripheral, for which we are using GPIO (GPIO2_IO00) to control the enable pin by toggling it between logic high and logic low.

To test the RS485 peripheral interface, I need to toggle through echo command the GPIO pin state (high or low). From the community page, I found a way to determine the GPIO number by inspecting the GPIO mappings. The following command displays the GPIO mapping:

root@imx93evk:/# cat /sys/kernel/debug/gpio

For our board, the output is as follows

root@imx93evk:/# cat /sys/kernel/debug/gpio

root@imx93-11x11-lpddr4x-pf0900-evk:~# cat /sys/kernel/debug/gpio
gpiochip0: GPIOs 512-543, parent: platform/43810000.gpio, 43810000.gpio:

gpiochip1: GPIOs 544-575, parent: platform/43820000.gpio, 43820000.gpio:
gpio-544 ( |cd ) in lo IRQ ACTIVE LOW

gpiochip2: GPIOs 576-607, parent: platform/43830000.gpio, 43830000.gpio:

gpiochip3: GPIOs 608-639, parent: platform/47400000.gpio, 47400000.gpio:

I'm currently using GPIO number 512 for GPIO2_IO00, and it is working fine. but, I want to understand more about how the GPIO numbers are calculated.

Specifically:

1. What is the exact GPIO number for GPIO2_IO00?
2. How can I calculate the GPIO number of GPIO2_IO00 using a formula?

Thank you for your guidance in advance.

Thanks & Regards,

Ravikumar

[LFGP]

dear,
take a look to the example:
if you want to export the GPIO1_IO_25;

# GPIO1_IO_25 means BANK=1 and ID=25
# GPIO_NUMBER = ((1 - 1) * 32 ) + 25 = 25

for the complete documentation use the next link
https://www.udoo.org/docs/Hardware_Accessories/GPIO_Pinout.html

for a kernel GPIO info
https://www.kernel.org/doc/Documentation/gpio/sysfs.rst

regards
LFGP

[gidame]

LMAO

[xacov]

I totally disagree with LFGP's explanation. A Linux driver cannot rely on a chip/chip manual. Here is what LFGP said, GPIO1_IO_25.

# GPIO1_IO_25 ​​means BANK=1 and ID=25

# GPIO_NUMBER = ((1 - 1) * 32 ) + 25 = 25

According to LFGP, GPIO2_IO00 should be 32,
((2 - 1) * 32 ) + 0 = 32
But Embedded-world says
“I'm currently using GPIO number 512 for GPIO2_IO00, and it is working fine. but, I want to understand more about how the GPIO numbers are calculated.”

This is the description of Documentation/gpio/sysfs.rst.
It is very obvious that the number of gpio in the Linux system depends on base and ngpio.
This is the log of Embedded-world.

"root@imx93-11x11-lpddr4x-pf0900-evk:~# cat /sys/kernel/debug/gpio
gpiochip0: GPIOs 512-543, parent: platform/43810000.gpio, 43810000.gpio:"

Because NXP's bsp wrote the order of gpio2 wrong in the device tree, it was displayed as gpiochip0 in Linux. But no matter what, it is calculated according to base + ngpio.

gpiochip0: GPIOs 512-543 32-bit serial numbers are from 512 to 543.

Documentation/gpio/sysfs.rs
GPIO controllers have paths like /sys/class/gpio/gpiochip42/ (for the
controller implementing GPIOs starting at #42) and have the following
read-only attributes:

/sys/class/gpio/gpiochipN/

"base" ...
same as N, the first GPIO managed by this chip

"label" ...
provided for diagnostics (not always unique)

"ngpio" ...
how many GPIOs this manages (N to N + ngpio - 1)

In addition, this article also explains how to calculate the gpio number.

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Accessing-GPIO-From-UserSpace/ta-p/11027...

I can't understand why Embedded-world  marked this answer as the correct answer, which caused misunderstanding to subsequent readers.

The gpio order in the device tree is wrong, causing Linux to display gpio2 as gpiochip0: GPIOs 512-543.

gpio2 is the first one in device tree.

	gpio2: gpio@43810000 {
			compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
			reg = <0x43810000 0x1000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clk IMX93_CLK_GPIO2_GATE>,
				 <&clk IMX93_CLK_GPIO2_GATE>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc 0 4 30>;
		};

		gpio3: gpio@43820000 {
			compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
			reg = <0x43820000 0x1000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clk IMX93_CLK_GPIO3_GATE>,
				 <&clk IMX93_CLK_GPIO3_GATE>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>,
				      <&iomuxc 26 34 2>, <&iomuxc 28 0 4>;
		};

		gpio4: gpio@43830000 {
			compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
			reg = <0x43830000 0x1000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clk IMX93_CLK_GPIO4_GATE>,
				 <&clk IMX93_CLK_GPIO4_GATE>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>;
		};

		gpio1: gpio@47400000 {
			compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
			reg = <0x47400000 0x1000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&clk IMX93_CLK_GPIO1_GATE>,
				 <&clk IMX93_CLK_GPIO1_GATE>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc 0 92 16>;
		};