Unable to reset MAC in IMX8MP

[Ben10]

Hi we are facing a problem in our board which was developed based on the IMX8MP board. In our board we are using DP83867 as the ethernet phy and we are getting a message as " unable to reset ENET_QOS". What should I do??

[Frantisek_Prochaska]

Hi @Ben10,
Your I2C6 setup looks promising. Can we compare it to Linux Device Tree?

[Ben10]

Hi @Frantisek_Prochaska 

Thanks for the reply

Pin Muxing and clock setting in Windows for I2C6:

IOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS = IOMUXC_MUX_ALT3 | IOMUXC_MUX_SION_DISABLED; //I2C6
IOMUXC_SW_MUX_CTL_PAD_SAI5_RXC = IOMUXC_MUX_ALT3 | IOMUXC_MUX_SION_DISABLED; //I2C6
IOMUXC_SW_PAD_CTL_PAD_SAI5_RXFS = I2C_PAD_CTRL; //I2C6
IOMUXC_SW_PAD_CTL_PAD_SAI5_RXC = I2C_PAD_CTRL; //I2C6
CCM_CCGR_I2C6 = 0x00;
CCM_TARGET_ROOT_I2C6 = CCM_TARGET_ROOT_MUX(0) | CCM_TARGET_ROOT_PRE_PODF(0) | CCM_TARGET_ROOT_POST_PODF(0) | CCM_TARGET_ROOT_ENABLE_MASK;
CCM_CCGR_I2C6 = 0x03;

Pin Muxing in ubuntu for I2C6:

pinctrl_i2c6: i2c6grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3 // value need to re-check
MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3 // value need to re-check
>;
};

/* IO Expander - 1 IRQ */
pinctrl_egpio1_int: egpio1intgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0xd6
>;
};

The last pin muxing in ubuntu is for interrupt pin.

[Frantisek_Prochaska]

Looks good to me. But compared to other i2c in BoartInit.c, You are setting SION as DISABLED. I would have to ask around why does it have to be enabled but quick search over Linux gives this hint:
fsl,pins = <
/* without SION i2c doesn't detect bus busy */
Could you try enabling SION?

[Ben10]

Hi @Frantisek_Prochaska 

Thanks for the reply

I have done SION configuration based on the IMX8MP reference manual 

I want to use the SAI5_RXFS pin as I2C6, so that's why I am disabling SION or else it would be used as SAI5_RXFS pin itself if SION is enabled.

[Frantisek_Prochaska]

The highlighted text in Reference Manual is the PAD name. It has nothing to do with MUX_MODE.

[Frantisek_Prochaska]

Looking into RM, You will also need to configure daisy chain registers.

[Ben10]

Hi @Frantisek_Prochaska 

Thank you so much for your help, I was finally able to fix it.

I still have one more issue related to ethernet, the ethernet works only randomly which means, it sometimes work when I power on the board and sometimes it does not work when I power on the board, sometimes it works after restarting the board and sometimes it doesn't work after restarting the board.

I don't know what could be the reason.

[Frantisek_Prochaska]

Hi @Ben10,
nice to hear it helped and ethernet works, at least occasionally. This is unconfirmed but supposedly "ConfigCmds" piece of code in Dsdt-Enet.asl is not applicable for QoS. So in case you want to initialize PHY, QoS driver has to be modified and rebuilt.
I don't have experience with PHY setup though so i can't help much here. You can still go over previous ideas from @Dhruvit or check other topics.

[Ben10]

Hi @Frantisek_Prochaska 

Thanks for the reply

In our board, the ENET QoS port is still not working, we have managed to only get the ENET port working.

But anyway I have to at least make one port work properly.

The ethernet phy in our board powers up through I2C6, so is there any possibility that the phy might power up before the MAC powers up??

[Frantisek_Prochaska]

Hi @Ben10,
Okay, that must be why you created so many similar topics. One for Ethernet and another for QoS.
I am not sure if I understand the problem correctly. I believe you have been able to:
1. Get I2C6 working in UEFI (BoardInit.c).
2. Setup the expander from BoardInit.c (this code runs before Windows)
3. Start working on PHY initialization. I would recommend to at least try the "ConfigCmds" section of Dsdt-Enet.asl before writing PHY init in BoardInit.c or in U-Boot.

[Ben10]

Hi @Frantisek_Prochaska 

Thanks for the reply

I checked the Ethernet connection in another board and it was working fine without an issue. But I have a question regarding the MAC address, in NXP board I observed that the MAC address for the ethernet is hard coded into the fuse, but in our board we have not hard coded the ethernet MAC address into the fuse, due to which we get the MAC address as 00:00:00:00:00:00 for both the ports. But even with MAC address as 00:00:00:00:00:00, the ENET port works. But we need to set a MAC address for the ethernet, so is it necessary to hard code the MAC address into the fuse or is there any other way to set mac address like random mac address in Windows 10 IoT (In ubuntu MAC address is not taken from the fuse but rather it is set randomly by U-boot which is used by the kernel)??

[Frantisek_Prochaska]

Hi @Ben,
the ethernet MAC can be obtained either from Fuses (which is easy to get wrong and you can't fix) or from Windows registry. I'd recommend searching for guide for the registry way.

Here's a random guide that does that:
https://www.top-password.com/blog/change-mac-address-on-windows/

[Ben10]

Hi @Frantisek_Prochaska 

In our board when I connect the ethernet cable to the ENET_QoS port, I get a log message as "WARNING Spurious Interrupt" and then the windows freezes and crashes and then restarts. But the ethernet phy is able to detect a connection change and we are getting correct phy register values. The warning message is coming from the interrupt service routine in the ENET_QoS driver in windows 10 IoT. The ENET_QoS port works fine in ubuntu.

[Ben10]

Hi @Dhruvit 

The ethernet phy that we use in our board which is the DP83867 works perfectly in linux with few changes in the dts file. In windows as you mentioned there are two ethernet drivers- Enet driver and Enet QoS driver. But it looked like the enet driver is not phy specific while the enet QoS driver has a phy specific initialisation part, but that part of the driver is not yet reached in the enet QoS driver as it is not able to do a MAC and DMA reset, while the problem in  enet driver is that it is reading the phy register wrongly as all the bits of the phy registers are 1.

There are only two changes between the NXP board and our board regarding the ethernet. 1. NXP uses RTL8211F while we use DP83867, 2. Both the phys in NXP share common mdio bus while we use a separate bus.

[Frantisek_Prochaska]

Hi Ben10,
this could easily be a bug in QoS driver - but this would need additional analysis.

However, from brief look at the code of the QoS driver - it has to be modified for new PHY. Based on your message, I imagine you are already debugging this ("net QoS driver is not able to do a MAC and DMA reset,").

Are you getting the "Unable to reset ENET_QOS" message?
I have asked around and the reason could be no RXC clock. Presumably this clock comes from PHY to the QoS. I believe QoS driver had to solve this by PHY configuration otherwise we would be hitting this error all the time.
But the easiest way to get this clock should be connecting ethernet cable to the PHY and a router or switch. PHY then can do auto-negotiation and start generating the clock. To check state of this clock you will need an oscilloscope.

[Ben10]

Hi @Frantisek_Prochaska 

Thanks for the reply

We have fixed the  " Unable to reset ENET_QOS" issue. It was because the phy wasn't getting power supply from an LDO which had to be enabled by an I2C GPIO expander. Now we are past that issue, now the phy is up and working, we are able to reset the MAC, read correct phy registers and also the phy is able to detect a link state change. But now the issue seems to be with the interrupt, when we connect an ethernet cable to the QoS port, we get a log message as "WARNING Spurious Interrupt" from the interrupt service routine in the Enet_QoS driver and the windows 10 IoT freezes completely and it crashes or we have restart the board to get it working. 

[Frantisek_Prochaska]

Hi @Ben10 ,
I have forgot to answer. Sorry about that. Have you been able to proceed with this issue?