U-boot DDR clock changes

[manjunathjoshi]

Hello All,

We have few boards which are having dual-lite processor.  I got the u-boot source but these boards have different DDR parts. That's why for some the u-boot is working and for some it is not. Can anybody let me know what should i look for in the data sheet of these DDR parts.

I am new to this u-boot source. Let me know if someone has encountered a similar problem.

Regards,

Manju

[igorpadykov]

Hi Manjunath

for new ddr chip one needs to run DDR tests

https://community.freescale.com/docs/DOC-96412

find new calibration coefficients, then modify dcd header with new

coefficients in uboot/../freescale..mx6sabresd/mx6dl_4x_mt41j128.cfg.

If necessary modify include/configs/mx6sabresd.h  (like ddr size),

then rebuild uboot.

Best regards

igor

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[manjunathjoshi]

Hello igorpadykov,

Thanks a lot for your reply. I ran the stress tester and got the following result

Current Tempareture: 61

============================================

DDR Freq: 396 MHz

ddr_mr1=0x00000000

Start write leveling calibration...

running Write level HW calibration

Write leveling calibration completed

    MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x0049004C

    MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x003C003C

    MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x001F001F

    MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x001F001F

Write DQS delay reult:

   Write DQS0 delay: 76/256 CK

   Write DQS1 delay: 73/256 CK

   Write DQS2 delay: 60/256 CK

   Write DQS3 delay: 60/256 CK

   Write DQS4 delay: 31/256 CK

   Write DQS5 delay: 31/256 CK

   Write DQS6 delay: 31/256 CK

   Write DQS7 delay: 31/256 CK

......

You expect me to get few more calibration values or this is fine?

If so then let me know .

Can you provide me sample calibration results ?

Thanks in advance,

Regards,

Manju

[igorpadykov · Accepted solution]

Hi Manjunath

for explanation and calibration values examples one can look at

Freescale i.MX6 DRAM Port Application Guide-DDR3

Best regards

igor