We have 2 distinct displays connected to lvds in separate mode.
Here's have the dtb:
&ldb {
lvds-channel@0 {
crtc = "ipu1-di0";
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: lcd12 {
clock-frequency = <40000000>;
hactive = <800>;
vactive = <600>;
hback-porch = <88>;
hfront-porch = <40>;
vback-porch = <23>;
vfront-porch = <39>;
hsync-len = <128>;
vsync-len = <4>;
bpp = <24>;
};
};
};
lvds-channel@1 {
crtc = "ipu1-di1";
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
status = "okay";
display-timings {
native-mode = <&timing7>;
timing7: lcd7 {
clock-frequency = <51206400>;
hactive = <1024>;
vactive = <600>;
hback-porch = <140>;
hfront-porch = <160>;
vback-porch = <20>;
vfront-porch = <12>;
hsync-len = <20>;
vsync-len = <3>;
};
};
};
};
Resolution and image is ok, but the frequency of the second display is set to 40Mhz, instead of the 51Mhz.
Debugging the kernel, i get the following output:
lvds0:
imx-ipuv3 2400000.ipu: dev 0 panel size = 800 x 600
imx-ipuv3 2400000.ipu: pixel clk = 40000000
imx-ipuv3 2400000.ipu: use special clk parent
imx-ipuv3 2400000.ipu: round pixel clk:39999998
imx-ipuv3 2400000.ipu: div:1
lvds1:
imx-ipuv3 2400000.ipu: dev 1 panel size = 1024 x 600
imx-ipuv3 2400000.ipu: pixel clk = 51205000
imx-ipuv3 2400000.ipu: use special clk parent
imx-ipuv3 2400000.ipu: round pixel clk:39999998
imx-ipuv3 2400000.ipu: div:1
imx-ipuv3 2400000.ipu: IPU DMFC DC HIGH RESOLUTION: 1(0~3), 5B(4,5), 5F(6,7)
So It seems the device tree is ok, but the clock is being set to the parent, that seems to be the same as the lvds0.
How can i fix this? it works well with some displays, that can tolerate this difference but not with others.
We tested this in both kernel 3.10.53 and 4.1.15.
