Hi,
We recently ported our custom imx51 board from Linux 2.6 to Linux 3.14.
Our display was rock solid with 2.6 no matter the length of the cable. Well with 3.14 we're having problems with the longer cable. The pixel clk is attenuated and has hiccups every n clock cycles depending on the frequency.
Upon further inspection of the IPU driver, the IPU parent is the ipu_gate clock.
In the older kernel we were using TVE (not external) as the parent clock to the IPU, but in the new kernel I'm having trouble figuring out where to set the IPU parent to TVE.
I tried to set the IPU parent in the imx51.dtsi file to TVE, but the choices are TVE gated or pre-divider so it doesn't work.
I tried reading through ipu-di.c and ipu-common.c
I tried different clock parent setups in clk-imx51-imx53.c, but no cigar.
Any help would be appreciated.
Hi,
I have checked L3.14.28 and I found the next configuration
tve: tve@63ff0000 { | |
compatible = "fsl,imx53-tve"; | |
reg = <0x63ff0000 0x1000>; | |
interrupts = <92>; | |
clocks = <&clks 69>, <&clks 116>; | |
clock-names = "tve", "di_sel"; | |
crtcs = <&ipu 1>; | |
status = "disabled"; |
};
And the corresponding clocks are
#define IMX5_CLK_TVE_GATE 69
#define IMX5_CLK_IPU_DI1_SEL 16
clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
And it seems that the mux clock can select other parent clocks. Have you tried those?
I need to check the ipu code to verify how the parents are chosen, but it seems that it is possible to choose others.
/Alejandro