The power domains with MIPI in IMX7S: 1V rail and decoupling caps

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The power domains with MIPI in IMX7S: 1V rail and decoupling caps

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ahall
Contributor I

We are using the IMX7Solo in a display project.

We use the MIPI interface to talk from the Solo to our display driver bridge chip. When the processor is powering up, all goes well until the LDO_1P0D is powered up. Then the processor hangs.

Stepping through the assembly code, it gets no further than enabling this regulator.

Enabling the current limit feature of the internal regulator, the processor can get past this stage. Enabling the brown out detect, shows that there is a brown out. However this internal power rail is only connected externally to the advised capacitors (as per the datasheet) and the two VDD_MIPI_1P0 pins, nothing else.

We have also found that if power up the 1V0 (with current limiting) then the internally switched 1V8 sometime later, the processor hangs again. So even with the current limiting on there, enabling the 1V8 rail after the 1V rail causes an issue with the supplies.

We are currently working in the belief that there is an issue where the inrush current on the 1V rail causes the power rail to drop significantly.

What can we do to limit the current draw on the 1V rail when we have no control over what it's connected to (other than the advised decoupling capacitors)?

We cannot see any advice on how the IMX7Solo decoupling requirements differ to the IMX7Dual, despite the fact that the Solo does not have the PCIe module, which (in the Dual) uses the 1V0 rail as well. This processor has no efuses blown, currently booting from the SD card.

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Yuri
NXP TechSupport
NXP TechSupport

ahall@triomotion.com 

Hello,

   Is it possible to look at the schematic?

Regards,

Yuri.

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ahall
Contributor I

Here is the relevant part of the schematic. Very similar to the SABER development board for the IMx7Dual, but using the IMx7Solo instead.

pastedImage_1.png

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Yuri
NXP TechSupport
NXP TechSupport

ahall@triomotion.com 

Hello,

   Schematic looks correct, assuming PCIe is not used.

As for the decoupling requirements - is it possible to apply the same

decoupling configuration as on the i.MX7 SABRE board. (Your scheme

follows the Hardware Development Guide.)

Regards,

Yuri.

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ahall
Contributor I

Hi Yuri,

I'm guessing that the lack of a reply means that you have no other idea for what to look for?

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

  Please check all the rest i.MX7 power supply voltages - if they are valid

and do not violate power up sequence.

Regards,

Yuri

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ahall
Contributor I

Hello Yuri,

The rails are valid and come up in the correct order.

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ahall
Contributor I

The PCIe is not used. We are using the IMx7 SOLO which does not have PCIe.

I have put on the caps to recreate the IMx7 DUAL decoupling as on the SABER board on our PCB. This has not solved the issue.

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232 Views
ahall
Contributor I

We have monitored the 1V0 and 1V8 rails which come out of the processor, and we have monitored the 1V8 rail which powers them both. They can be seen in this image.

IMG_20200709_132838.jpg

It is clear that the two rails come up, and that the input 1V8 rail has a very slight reduction on it when the output rails are switched on. But no where near enough to cause a brown out. But still the processor hangs completely as soon as the output rails are enabled.

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