The flip frequency configuration problem of gpio_output on the IMX8MM scheme

[jack_huang1]

Dear,

        I encountered some issues while debugging the imx8mm M4. I wanted a 300ns IO flip and used the official SDK. I removed the delay in the gpio_output routine and flipped the IO directly, corresponding to GPO4-IO0; Using an oscilloscope test, it was found that theoretically the cycle is 5ns, and the main frequency of the M4 core is 400MHz. However, in reality, it was found that the frequency of IO flip is above 1us. At the same time, using the NXP IMX8MM EVK board for testing, the GPO3-IO2 pins were flipped, and the delay was removed. Using an oscilloscope for testing, a cycle of 400ns could be achieved. May I ask: What is the possible reason? Do you have any IO routines related to NXP that you can refer to? thank you!
Figure 1 shows the waveform of the self-developed board test.
Figure 2 is a screenshot of debugging
Figure 3 is a screenshot of software configuration
Figure 4 shows the NXP IMX8MM EVK environment
Figure 5 shows the waveform of NXP IMX8MM EVK test

       Best Regards!

[Zhiming_Liu]

Hello,

The toggling speed on baremetal CM4(400MHz) we tested is 3.5 MHz(HIGH-->LOW=285.7ns), codes were performed with direct writes to GPIOn.DR.

Here is pad configuration.

• 11X X6 — Drive strength X6
• 1X FAST — Select fast slew rate

What do you mean here for '300ns IO flip"? high->low? or high->low->high?

Best Regards,
Zhiming

[jack_huang1]

Dear；

         IO flip is high->low->high,  where can I configure the pad configuration? Thank you!


   Best Regards！

[Zhiming_Liu]

Hello,

In BOARD_InitPins function, you could use different IOMUXC_SW_PAD_CTL_PAD_xxx flags in  IOMUXC_SetPinConfig

void BOARD_InitPins(void) {                                /*!< Function assigned for the core: Cortex-M7F[m7] */

    IOMUXC_SetPinMux(IOMUXC_UART4_RXD_UART4_RX, 0U);

    IOMUXC_SetPinConfig(IOMUXC_UART4_RXD_UART4_RX,

                        IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |

                        IOMUXC_SW_PAD_CTL_PAD_PE_MASK);

    IOMUXC_SetPinMux(IOMUXC_UART4_TXD_UART4_TX, 0U);

    IOMUXC_SetPinConfig(IOMUXC_UART4_TXD_UART4_TX,

                        IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |

                        IOMUXC_SW_PAD_CTL_PAD_PE_MASK);

}

Best Regards,
Zhiming