Switching Exception Level EL3 to EL1 in IMX8M

[Hariharan1]

in Arm Cortex A53. I was competed Enabled Quad core, now I want to trigger interrupt. The interrupt present in exception level 1 (EL1). There is an issue while I am switching EL3 to EL1. When I jump to el1 entry symbol it is going to hanging in synchronous exception handler(cxsynx). Where I did mistake in this scenario.kindly let me know

[Bio_TICFSL]

Hello,

EL1 is the level that priveldged parts of the OS kernels use, so for example, Linux Kernel code will run with EL1 priveledges

AArch64 has a dedicated register (CurrentEL) that we can read to figure out our the current EL. CurrentEL is a system register and we should use a special instruction mrs to read such system registers, so the code starts like this:

mrs x0, CurrentEL

This instruction will read the content of the CurrentEL to a general purpose register x0. The register CurrentEL is a 64-bit one, but most of the bits are hardwired to be 0 and only bits 2 and 3 contain the actual EL value

So now we need to test if the value we read from CurrentEL is:

• equal to 8 - nothing for us to do, we are already at EL2
• smaller than 8 - to late for us to do anything, we are in EL1 or EL0
• higher than 8 - we are in EL3 and have to jump to EL2.

NOTE: remember that the EL value is stored in bits 2 and 3, that’s why we compare to 8 and not to 2 (8 is just 2 shifted by 2 bits).

Putting everything together we get the following:

    mrs x0, CurrentEL
    cmp x0, #0b1000  // remember the EL value is stored in bits 2 and 3
    beq in_el2
    blo in_el1

in_el3:
    // Put code switching from EL3 to EL2 here

in_el2:
    // This code will run at EL2

in_el1:
    // We are in EL0 or EL1, so we probably should report an error here

Regards

[Hariharan1]

mov x3, #(SCR_EL3_RW | \
SCR_EL3_SMD | \
SCR_EL3_NS) // Set NS bit, to access Non-secure registers
msr SCR_EL3, x3
mov x0, #(HCR_EL2_RW)
msr hcr_El2, x0
// Initialize the SCTLR_EL1 register before entering EL1.
MSR SCTLR_EL1, XZR

mov x0, #15
msr ICC_SRE_EL2, x0
isb
msr ICC_SRE_EL1, x0 // Non-secure copy of ICC_SRE_EL1

//
// Get the current state and exception level
mrs x0, CurrentEL
and x1, x0, #0xC
lsr x1, x1, #2



// Set the target PC_EL1 to the exception handler address
adr x3, el1_entry_aarch64
msr elr_el3, x3

mrs x1, SPSR_EL3
msr daifset, #0xF

mrs x2, SPSR_EL3
mov x2, #0x3C5
msr SPSR_EL3, x2

//Enabling IRQ by clearing bit
mrs x0, daif
bic x0, x0, #(1 << 7)
msr daif, x0

//Disabling IRQ by masking bit
mrs x0, daif
orr x0, x0, #(1 << 7)
msr daif, x0

// Switch to EL1
eret

el1_entry_aarch64:
ldr x0, =__stack
Mov sp, x0
bl main

This is my code. I was checked currentel register, it contain exception level 3(EL3). Once jump into el1entry function after that CPU gets hanging. Not even check esr_el1 register. Can you check it, what I need to change in this code?