State of GPIO when i.MX7ULP is in VLLS mode

[ko-hey]

Hi all,

I have a question about state of GPIO when it's in VLLS mode.

According to the Table 27-8 of reference manual, RGPIO2P0 is power gated.

So I guess that it can't keep the state before entering VLLS mode.

Am I correct ?

Ko-hey

[terry_lv]

Hi,

  When entering VLLS mode, GPIO state of PTA, PTB, PTC, PTE, PTF should be kept.

  Except for PTD, it can't keep the GPIO state in VLLS.

  Thanks!

Regards

Terry

[ko-hey]

hi TerryLv‌,

Thank you for reply.

I can't understand the meaning of your answer.

Are you concerned about voltage ?

Ko-hey

[terry_lv]

Hi Ko-hey,

  I mean the voltage level on GPIO port.

  Don't you mean it?

  Thanks!

Regards

Terry

[igorpadykov]

Hi Ko-hey

>According to the Table 27-8 of reference manual, RGPIO2P0 is power gated.

>So I guess that it can't keep the state before entering VLLS mode.

>Am I correct ?

yes correct.

Best regards
igor
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[ko-hey]

Hi igorpadykov‌,

Thank you for reply.

Is it same as RGPIO2P1 ?

Ko-hey

[igorpadykov]

Hi Ko-hey

>Is it same as RGPIO2P1 ?

yes it is the same.

Best regards
igor