Hi all,
I have a question about state of GPIO when it's in VLLS mode.
According to the Table 27-8 of reference manual, RGPIO2P0 is power gated.
So I guess that it can't keep the state before entering VLLS mode.
Am I correct ?
Ko-hey
Hi,
When entering VLLS mode, GPIO state of PTA, PTB, PTC, PTE, PTF should be kept.
Except for PTD, it can't keep the GPIO state in VLLS.
Thanks!
Regards
Terry
hi TerryLv,
Thank you for reply.
I can't understand the meaning of your answer.
Are you concerned about voltage ?
Ko-hey
Hi Ko-hey,
I mean the voltage level on GPIO port.
Don't you mean it?
Thanks!
Regards
Terry
Hi Ko-hey
>According to the Table 27-8 of reference manual, RGPIO2P0 is power gated.
>So I guess that it can't keep the state before entering VLLS mode.
>Am I correct ?
yes correct.
Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
Hi Ko-hey
>Is it same as RGPIO2P1 ?
yes it is the same.
Best regards
igor