Startup for PF1550+i.MX6ULL power-on

[yuji_matsunami]

Hi,
We would like to use PF1550 for our implementation with i.MX6ULL.
The SW1 starts at the same timing as the SW1 against VLDO3 at power-on. (Difference less than 0.1ms)
Looking at the following Figure 27 on the PF1550 datasheet, I think the output is delayed by tD3(1.5 -6.0ms).
Is the behavior when the power is turned on different from the datasheet?
The PWRON pin is always High and the STANDBY pin is always Low.

[john_phillippe]

I don't quite understand your question.  Are you seeing behavior on your device that is different than what is described in the datasheet?

[yuji_matsunami]

There is no power up delay difference between VLDO3 and SW1.(Difference less than 0.1ms)

[john_phillippe]

In the case you highlighted there are three periods of Td3 (0.5ms typ) which would give a typical delay of 1.5ms if OTP_SEQ_CLK_SPEED=0, and 6ms total delay if OTP_SEQ_CLK_SPEED=1.