Specific question regarding imx6 IPU DI

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Specific question regarding imx6 IPU DI

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eugeniur
Contributor II

Dear community members,


I need an opinion from the users experienced in imx6 IPUv3 kernel driver to solve a specific problem in our application.

Our development board is Sabre Lite from Boundary Devices.

In short, our targeted device can be seen as a tablet with HDMI input.

We want to combine 2 video streams (please, review the attached image):

- HDMI video stream (downscaled to 1280x800, set to 60fps and converted to RGB888);

- GUI video stream generated by iMX6 (same format as above);

The intention is to put the GUI above the HDMI picture (overlay done externally by FPGA) and to display the result on LCD.

Currently the problem is to have the pixel information coming to FPGA in synchronous manner (pixel N from source1 and pixel N from source2 at the same time), in order to avoid the need for memory at FPGA level.

Basically, in my understanding, this would be possible if driving the imx6 IPU by external clock and syncs (H/V).

According to imx6 reference manual it should be possible. However, the community threads discussing the ASYNC IPU DI functionality are mainly focused on system-80 or system-68K protocols, which are not required in our application.

Could someone provide a starting point for me to go on and implement the feature in the IPU driver.

What would be the workload for this?

Best regards,

Eugeniu.

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1 Solution
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karina_valencia
NXP Apps Support
NXP Apps Support
Re: Specific question regarding imx6 IPU DI

Chih Chieh TuEmployee

I guess you are saying, you will have two IPU DI output to your FPGA, and how to sync these two DIs.

My suggestion is,

1. Two DIs are using the same pixel clock tree

2. Setting IPU in advance

3. One time write to enable two IDMAC, to start two IPU idmac channel.

i.e., ipu_idmac_write(ipu,  reg | 0x1 << 23 | 0x1 << 28, IDMAC_EN);


Hope it helps.

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karina_valencia
NXP Apps Support
NXP Apps Support
Re: Specific question regarding imx6 IPU DI

Chih Chieh TuEmployee

I guess you are saying, you will have two IPU DI output to your FPGA, and how to sync these two DIs.

My suggestion is,

1. Two DIs are using the same pixel clock tree

2. Setting IPU in advance

3. One time write to enable two IDMAC, to start two IPU idmac channel.

i.e., ipu_idmac_write(ipu,  reg | 0x1 << 23 | 0x1 << 28, IDMAC_EN);


Hope it helps.

View solution in original post

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eugeniur
Contributor II

Hi Karina,

Thanks for feedback!

I have already begun studying IPU IDMAC driver.

Hope to make some signs of progress soon.

Regards!