Software defect about LCDIF clock

[PeterChan]

Dear All,

In MX28 BSP release L2.6.35_10.12.01, it is a software defect that the value at HW_CLKCTRL_DIS_LCDIF DIV field may be cleared by mistake when "lcdif" clock is enabled. This can lead to LCDIF malfunction. Please apply the change below to fix this problem.

Thanks! 

diff --git a/arch/arm/mach-mx28/clock.c b/arch/arm/mach-mx28/clock.c
index 9797d1f..e732138 100644
--- a/arch/arm/mach-mx28/clock.c
+++ b/arch/arm/mach-mx28/clock.c
@@ -1199,7 +1199,7 @@ static struct clk dis_lcdif_clk = {
        .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF,
        .busy_bits = 29,
        .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF,
-       .enable_bits = 31,
+       .enable_bits = BM_CLKCTRL_DIS_LCDIF_CLKGATE,
        .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ,
        .bypass_bits = 14,
        .get_rate = lcdif_get_rate,

[ask]

Hi PeterChan,

           I am using llinux-2.6.35.3  mx28 bsp. I am not seeing the code change you mentioned. Where can I see the im28 bsp release version.

Here is the dis lcdif structue.

static struct clk dis_lcdif_clk = {

.parent = &pll_clk[0],

.enable = mx28_raw_enable,

.disable = mx28_raw_disable,

.scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF,

.scale_bits = 0,

.busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF,

.busy_bits = 29,

.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF,

.enable_bits = 31,

.bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ,

.bypass_bits = 14,

.get_rate = lcdif_get_rate,

.set_rate = lcdif_set_rate,

.set_parent = lcdif_set_parent,

.flags = CPU_FREQ_TRIG_UPDATE,

};

I interfaced tm035kd panel to my board and am seeing some glitches on right side of the display. This malfunction is related to with above fix. Please let me know.

[PeterChan]

I am terribly sorry the fix has not committed to any branches yet, though defect # ENGR00331323 has assigned. Please apply the fix manually.