Settings for DDR

[ko-hey]

Hi all,

I have question about settings for DDR

1.

The comments in the [Register Configuration] sheet J73 and J77 in the following file are described in the following two stages.

https://community.nxp.com/docs/DOC-105963

1st step: Settings other than PWDT_0 and PWDT_1

2nd step: PWDT_0, PWDT_1 settings

The reference manual does not contain instructions to set two levels, but does user need to set two steps ?

If necessary, please tell us how much time between 1st step and 2nd step should be left.

2.

There are two registers that can set the ODT value of DRAM_DATA [63: 0]. When setting the ODT value, can you tell which register's ODT value will be reflected?

・IOMUX C_SW_PAD_CTL_GRP_TERM_CTL 0 to 7 [ODT] field

・MPODTCTRL ODTx_INT_RES field

Ko-hey

[Yuri]

Hello,

  Below are comments regarding the issue.

1.

  Generally customers can follow section 44.4.2 (MMDC initialization) of the recent

i.MX 6Dual/6Quad Reference Manual, Rev. 5, 06/2018. The i.MX6DQ SABRE SDP/B DDR3

Register Programming Aid, published in Community, provides the tool with more detailed

explanation.

https://community.nxp.com/docs/DOC-105963 

  Customers can look at the example of memory initialization script, which

is presented on the “RealView .inc file” sheet of the RPA Excel file.

  Note, the mentioned delay between the two stages is not specified.

2.

  It is recommended to use only MMDC_MPODTCTRL register to configure ODT of i.MX6.

Have a great day,
Yuri.

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