Security register usage in FlexSPI peripheral in IMX RT1170

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Security register usage in FlexSPI peripheral in IMX RT1170

986 次查看
anasnadukkandiyil
Contributor III

In IMXRT1170 FlexSPI peripheral, we are interfacing NOR flash W25Q512NW-DTR .We need to access the secure register for storing MAC address. Currently, we are using NOR flash driver adapted from SDK_2_10_0_EVKB-IMXRT1050. We are trying to create a lookup table for the commands 44h, 42h, 48h (Erase, Program, Read security registers). But the current NOR flash uses all the 64 slots except instruction indices 10 and 14. Is there any sample code or manual to do the same?

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964 次查看
anasnadukkandiyil
Contributor III

I added commands for Security register erase, read and  write as 10,12 and 14 indices respectively in the lookup table . Security register address 0x100 is used for read and write. The lookup table for these commands  are added as below.

config->lookupTable[4U * NOR_CMD_LUT_SEQ_IDX_SECURITY_ERASE] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, kSerialNorCmd_SecurityErase, kFLEXSPI_Command_RADDR_SDR,
kFLEXSPI_1PAD, address_bits);

config->lookupTable[NOR_CMD_LUT_SEQ_IDX_SECURITY_READ * 4U] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, kSerialNorCmd_ReadSecurityReg1, kFLEXSPI_Command_RADDR_SDR,
kFLEXSPI_1PAD, address_bits);
config->lookupTable[NOR_CMD_LUT_SEQ_IDX_SECURITY_READ * 4U + 1U] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_MODE8_SDR, kFLEXSPI_1PAD, mode_cycles, kFLEXSPI_Command_DUMMY_SDR,
kFLEXSPI_1PAD, 8);
config->lookupTable[NOR_CMD_LUT_SEQ_IDX_SECURITY_READ * 4U + 2U] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, 0, 0, 0);

 

config->lookupTable[4U * NOR_CMD_LUT_SEQ_IDX_SECURITY_PAGEPROGRAM] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, kSerialNorCmd_WriteSecurityReg1,
 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
 config->lookupTable[4U * NOR_CMD_LUT_SEQ_IDX_SECURITY_PAGEPROGRAM + 1U] = FLEXSPI_LUT_SEQ(
 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0);

addr_bits value is configured to be 32. Added APIs for erase,program and read. But the value read is not correct as the expected value.

Is the above values correct for security registers?

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jeremyzhou
NXP Employee
NXP Employee

Hi @anasnadukkandiyil ,
Thanks for your reply.
I was wondering if you can upload the complete demo code, further, whether you ever use the logic analyzer or oscilloscope to visualize the waves, if not, please give it a try.
Have a great day,
TIC

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jeremyzhou
NXP Employee
NXP Employee

Hi @anasnadukkandiyil ,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1) Is there any sample code or manual to do the same?
-- Please refer to flexspi_nor_polling_transfer demo to learn how to update the LUT.
TIC

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