I understand the DVFS concept with Vdd, but how does it work with Vcc? With Vdd, we just slow the CPU clock, and therefore can lower the voltage and save power while we aat idle or in background.
But with Vcc, we cannot lower the FEC or USB or UART clocks without causing the these systems to fail because they need specific clock rates. How does one save power with DVFS for Vcc?
The DVFS includes CORE and PER, the CORE means CPU, and PER means peripheral, once there is no high speed devices running, dvfs per driver can lower bus's freq, includes DDR, AXI, AHB etc., and with lower bus freq, Vcc can be lower as well.
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The DVFS includes CORE and PER, the CORE means CPU, and PER means peripheral, once there is no high speed devices running, dvfs per driver can lower bus's freq, includes DDR, AXI, AHB etc., and with lower bus freq, Vcc can be lower as well.
